AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 2

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

Asynchronous DSI Connections and Timings
The DSI operates in either asynchronous or synchronous mode. In asynchronous mode, the DSI functions in an
SRAM-like mode that does not require the host to supply a clock to the slave MSC8102. In synchronous mode, the
DSI functions as an SSRAM-like interface and operates with a host-supplied clock. This application note focuses
on the throughput for the asynchronous DSI mode. Asynchronous mode does not support burst transfers. However,
the DSI has a write buffer and a read buffer to help increase the overall throughput because they allow the host to
perform successive accesses without the overhead of wait states.
The DSI asynchronous throughput is affected by many parameters and conditions. First, the DSI shares external
buses with other MSC8102 resources, such as the DMA controller and the TDMs. If the MSC8102 device uses
these resources at the same time as the DSI, the DSI may have to wait to be granted access to the bus, which affects
overall throughput. In addition, the DSI drives an acknowledge signal to indicate when it has completed a read or
write transaction. The host must wait until the DSI stops driving the transfer acknowledge before the next access.
In most cases, the host processor needs to synchronize the transfer acknowledge with an internal clock, which adds
latency to the access and reduces the throughput. The host processor memory controller timings also affect the
throughput. Relaxing the timings greatly limits DSI performance. On the other hand, optimizing the host timings
can result in improved DSI performance. Also, the DSI throughput depends on the MSC8102 local bus frequency.
For example, if the local bus operates at 50 MHz, the throughput is less than if the local bus operates at 100 MHz.
However, the DSI limits the DSI operational frequency to 70 MHz even if the local bus operates at 100 MHz.
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The throughput calculations discussed here are based on DSI timings on a logic analyzer. To understand the
throughput calculations, the asynchronous connections and timings must be considered.
2.1 MSC8101 to MSC8102 DSI Connection
The asynchronous throughput performance measurements are taken using an MSC8102 Application Development
System (ADS) board. This board has an MSC8101 host processor that connects to the MSC8102 slave device as
shown in Figure 1. The system bus on the MSC8101 host processor connects to the DSI on the MSC8102 slave as
if it were an external memory.
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Asynchronous DSI Connections and Timings
MSC8101 Host
Figure 1. MSC8101 to MSC8102 Physical Connection
UPMWAIT
A[11–29]
RAS/POE
MSC8102 Asynchronous DSI Throughput, Rev. 1
D[0–63]
A[7–10]
PWE0
PWE1
PWE2
PWE3
PWE4
PWE6
PWE5
PWE7
CS4
CS3
MSC8102 Slave
HD[0–63]
HA[11–29]
HCID[0–3]
HCS
HBCS
HTA
HRW
HWBS0
HWBS1
HWBS2
HWBS3
HWBS4
HWBS5
HWBS6
HWBS7
Freescale Semiconductor