AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 10

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

Actual Throughput
4.6 Host DMA Write Throughput
The maximum DSI host DMA write performance is calculated from the timing results shown in Figure 9. The
figure shows the host clock, address lines, chip select, write enable strobe, and the transfer acknowledge signal.
The throughput for consecutive host DMA write accesses is calculated to be 71.98 MB/s, which translates into
approximately 6.99 MSC8101 bus clock cycles with a 66 MHz clock. This value is averaged over four consecutive
write transactions. As for the host DMA read transactions, the host DMA write accesses reduce the latency when
writing to consecutive memory locations.
4.7 Broadcast Host DMA Write Throughput
The maximum host DMA broadcast write performance measurements are based on timings obtained using a logic
analyzer. Figure 10 shows the results from the logic analyzer during consecutive accesses to M2 memory. The host
clock runs at 66 MHz and is the MSC8101 system bus clock by which the UPM controls the external memory
accesses. In addition, the figure illustrates the address lines, chip select, and write enable signal. The
signal is not needed in the broadcast write as it was in the normal host DMA read and write transactions. The
throughput for consecutive broadcast host DMA write accesses is calculated to be 91.37 MB/s, which translates
into approximately 5.5 MSC8101 bus clock cycles, which is averaged over four consecutive write transactions.
The broadcast host DMA write is clearly faster than the normal host DMA write transaction because a transfer
acknowledge is not necessary.
10
System Bus Clock
System Bus Clock
HTA/UPMWAIT
HWBS0/PWE0
HTA/UPMWAIT
HRW/POE
HCS/CS4
HCS/CS4
Address
Address
MSC8102 Asynchronous DSI Throughput, Rev. 1
Figure 8. Asynchronous Host DMA Read
Figure 9. Asynchronous Host DMA Write
Freescale Semiconductor
UPMWAIT