AN2505 Freescale Semiconductor / Motorola, AN2505 Datasheet - Page 4

• Manufacturer Part Number: AN2505
• Description: MSC8102 Asynchronous DSI Throughput
• Manufacturer: Freescale Semiconductor / Motorola

Asynchronous DSI Connections and Timings
2.2.2 DSI Write Timings
Figure 3 shows the timings for an asynchronous DSI write transaction as indicated in the MSC8102 Technical
Data sheet. When the memory controller on the host processor is programmed, the MSC8102 write timing
specifications must be met to implement the write transaction properly. A write transaction is almost exactly the
same as a read transaction. For a write transaction, the address of the memory location or register must be driven
first. Then, the host issues a chip select to enable the MSC8102 DSI. As with the read transaction, the
signals are sampled to determine which MSC8102 DSI is selected. When the
value in the DCIR register, the DSI is accessed. The host continues the transaction by asserting the
and then later deasserting the signal. Meanwhile, the data can be sampled by the MSC8102 DSI. The typical
handshaking process is complete when the MSC8102 drives the
transfer is complete.
2.2.3 DSI Broadcast Write Timings
Figure 4 illustrates the timings for an asynchronous DSI broadcast write transaction as indicated in the MSC8102
Technical Data sheet. The host processor memory controller timings must meet the MSC8102 broadcast write
timings in the MSC8102 Technical Data sheet. A broadcast write is a write to multiple DSPs at the same time. The
timings are the same as for a normal write transaction except that the
DSPs share the same signals. If the host processor broadcasts data to each DSP and the DSI from one DSP drives
the
increases DSI throughput for broadcast writes because the host processor does not have to wait to synchronize the
transfer acknowledge signal internally. The rest of the broadcast write transaction is the same as a normal write
transaction to the DSI.
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HTA
signal, the host processor cannot determine which DSP drove the
HA[11–29]
HCID[0–4]
HD[0–63]
HWBSn
HRDS
HDST
HTA
HTA
HRW
HCS
MSC8102 Asynchronous DSI Throughput, Rev. 1
Figure 3. DSI Asynchronous Write Timings
100
108
106
112
201
HTA
signal to notify the host processor that the data
HTA
202
HTA
signal is not needed because multiple
111
101
102
HCID[0–3]
signal. The absence of an
109
110
signals match the CHIPID
Freescale Semiconductor
HWBS
HCID[0–3]
HTA
signal
signal