FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 107

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

Register Behavior
Table 43 illustrates the AT and PS/2 (including
Model 30) configuration registers available and the
type of access permitted.
software transparency, access to all the registers
must be maintained. As Table 43 shows, two sets
of registers are distinguished based on whether
their access results in the part remaining in
powerdown state or exiting it.
Access to all other registers is possible without
awakening the part.
accessed during powerdown without changing the
status of the part. A read from these registers will
reflect the true status as shown in the register
description in the FDC description. A write to the
part will result in the part retaining the data and
subsequently reflecting it when the part awakens.
Accessing the part during powerdown may cause
an increase in the power consumption by the part.
The part will revert back to its low power mode
when the access has been completed.
These registers can be
In order to maintain
107
Pin Behavior
The FDC37M81x is specifically designed for
systems in which power conservation is a primary
concern.
during powerdown very important.
The pins of the FDC37M81x can be divided into
two major categories: system interface and floppy
disk drive interface. The floppy disk drive pins are
disabled so that no power will be drawn through
the part as a result of any voltage applied to the
pin within the part's power supply range. Most of
the system interface pins are left active to monitor
system accesses that may wake up the part.
System Interface Pins
Table 44 gives the state of the system interface
pins in the powerdown state. Pins unaffected by
the powerdown are labeled "Unchanged". Input
pins are "Disabled" to prevent them from causing
currents internal to the FDC37M81x when they
have indeterminate input values.
This makes the behavior of the pins