FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 18

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

STATUS REGISTER B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 andModel 30 modes.
are held in a high impedance state for a read of address 3F1.
PS/2 Mode
BIT 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset.
BIT 1 MOTOR ENABLE 1
Active high status of the MTR1 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset. Note: In the
FDC37M81x only one drive is available at the FDD
interface.
BIT 2 WRITE GATE
Active high status of the WGATE disk interface
output.
BIT 3 READ DATA TOGGLE
Every inactive edge of the RDATA input causes
this bit to change state.
The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7
RESET
COND.
7
1
1
6
1
1
DRIVE
SEL0
5
0
TOGGLE
WDATA
4
0
18
BIT 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes
this bit to change state.
BIT 5 DRIVE SELECT 0
Reflects the status of the Drive Select 0 bit of the
DOR (address 3F2 bit 0). This bit is cleared after
a hardware reset and it is unaffected by a software
reset.
BIT 6 RESERVED
Always read as a logic "1".
BIT 7 RESERVED
Always read as a logic "1".
TOGGLE
RDATA
3
0
WGATE
2
0
MOT
EN1
1
0
MOT
EN0
0
0