FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 94

• Manufacturer Part Number: FDC37M81x
• Description: PC98/99 Compliant Enhanced Super I/O Controller
• Manufacturer: SMSC Corporation

Register Definitions
The register definitions are based on the standard
IBM addresses for LPT. All of the standard printer
ports are supported.
attach to an upper bit decode of the standard LPT
port
Note 1: These addresses are added to the parallel port base address as selected by configuration register
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
NAME
or jumpers.
*Refer to ECR Register Description
MODE
000
001
010
011
100
101
110
111
definition
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the configuration registers)
Reserved
Test mode
Configuration mode
ADDRESS (Note 1)
The additional registers
+401h R/W
+000h R/W
+000h R/W
+001h R/W
+002h R/W
+400h R/W
+400h R/W
+400h R/W
+402h R/W
+400h R
Table 37 - ECP Register Definitions
Table 38 - Mode Descriptions
to
DESCRIPTION*
94
ECP MODES
avoid conflict with standard ISA devices. The port
is equivalent to a generic parallel port interface
and may be operated in that mode. The port
registers vary depending on the mode field in the
ecr. The table below lists these dependencies.
Operation of the devices in modes other that those
specified is undefined.
DATA and ecpAFifo PORT
ADDRESS OFFSET = 00H
000-001
011
010
011
110
111
111
All
All
All
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
FUNCTION