FDC37M81x SMSC Corporation, FDC37M81x Datasheet - Page 148

Manufacturer Part Number

FDC37M81x

Description

PC98/99 Compliant Enhanced Super I/O Controller

Manufacturer

SMSC Corporation

Datasheet

1.FDC37M81X.pdf (198 pages)

Note:

Note 1: The DMA (0x74) default address for logical device 0 (FDD) is 0x02 and for logical device 3 is

DMA Channel

Select

Default = 0x04

or 0X02

(Note 1)

on VCC POR,

VTR POR, SOFT

RESET and

HARD RESET

NAME

A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :

For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.

For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.

DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.

0x04.

Table 57 - DMA Channel Select Configuration Register Description

REG INDEX

0x74 (R/W)

Bits[2:0] select the DMA Channel.

0x00= Reserved

0x01= DMA1

0x02= DMA2

0x03= DMA3

0x04-0x07= No DMA active

148

DEFINITION

STATE