LM3S102 Luminary Micro, Inc, LM3S102 Datasheet
LM3S102
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LM3S102 Summary of contents
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... DS -LM3S 102- 03 LM3S102 Microcontroller C opyr ight © 2006 Lumi nary Micro , Inc ATA SHEET ...
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... Copyright © 2006 Luminary Micro, Inc. All rights reserved. Stellaris and the Luminary Micro logo are trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. ...
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... Interrupts ............................................................................................................................. 35 5. JTAG Interface .................................................................................................................... 38 5.1 Block Diagram ..................................................................................................................................... 39 5.2 Functional Description ......................................................................................................................... 39 5.2.1 JTAG Interface Pins............................................................................................................................. 40 5.2.2 JTAG TAP Controller ........................................................................................................................... 41 5.2.3 Shift Registers ..................................................................................................................................... 42 5.2.4 Operational Considerations ................................................................................................................. 42 5.3 Initialization and Configuration............................................................................................................. 43 5.4 Register Descriptions........................................................................................................................... 44 5.4.1 Instruction Register (IR) ....................................................................................................................... 44 5.4.2 Data Registers ..................................................................................................................................... 46 6. System Control.................................................................................................................... 48 6.1 Functional Description ......................................................................................................................... 48 6.1.1 Device Identification............................................................................................................................. 48 July 6, 2006 Preliminary LM3S102 Data Sheet 3 ...
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Table of Contents 6.1.2 Reset Control ....................................................................................................................................... 48 6.1.3 Power Control ...................................................................................................................................... 51 6.1.4 Clock Control ....................................................................................................................................... 51 6.1.5 System Control .................................................................................................................................... 53 6.2 Initialization and Configuration............................................................................................................. 53 6.3 Register Map ....................................................................................................................................... 54 6.4 Register Descriptions........................................................................................................................... 55 7. Internal Memory ...
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... Register Map ..................................................................................................................................... 298 14.5 Register Descriptions......................................................................................................................... 298 15. Pin Diagram ....................................................................................................................... 306 16. Signal Tables ..................................................................................................................... 307 17. Operating Characteristics ................................................................................................ 314 18. Electrical Characteristics ................................................................................................. 315 18.1 DC Characteristics ............................................................................................................................. 315 18.1.1 Maximum Ratings .............................................................................................................................. 315 18.1.2 Recommended DC Operating Conditions ......................................................................................... 315 18.1.3 On-Chip Linear Drop-Out (LDO) Regulator Characteristics............................................................... 316 18.1.4 Power Specifications ......................................................................................................................... 317 July 6, 2006 Preliminary LM3S102 Data Sheet 5 ...
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Table of Contents 18.1.5 Flash Memory Characteristics ........................................................................................................... 317 18.2 AC Characteristics ............................................................................................................................. 318 18.2.1 Load Conditions ................................................................................................................................. 318 18.2.2 Clocks ................................................................................................................................................ 318 18.2.3 Analog Comparator............................................................................................................................ 319 2 18.2.4 I C...................................................................................................................................................... 319 18.2.5 Synchronous Serial Interface (SSI) ................................................................................................... 321 18.2.6 ...
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... List of Figures Figure 1-1. Stellaris High-Level Block Diagram ........................................................................................... 23 Figure 1-2. LM3S102 Controller System-Level Block Diagram ................................................................... 29 Figure 2-1. CPU Block Diagram .................................................................................................................. 31 Figure 2-2. TPIU Block Diagram .................................................................................................................. 32 Figure 5-1. JTAG Module Block Diagram .................................................................................................... 39 Figure 5-2. Test Access Port State Machine ............................................................................................... 42 Figure 5-3. IDCODE Register Format.......................................................................................................... 46 Figure 5-4. BYPASS Register Format ......................................................................................................... 46 Figure 5-5. ...
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List of Figures Figure 13-12. Master Burst SEND after Burst RECEIVE............................................................................... 270 Figure 13-13. Slave Command Sequence..................................................................................................... 271 Figure 14-1. Analog Comparator Module Block Diagram ............................................................................ 295 Figure 14-2. Structure of Comparator Unit................................................................................................... 296 Figure 14-3. Comparator Internal Reference Structure ...
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... Clock Characteristics............................................................................................................... 318 Table 18-8. Analog Comparator Characteristics......................................................................................... 319 Table 18-9. Analog Comparator Voltage Reference Characteristics.......................................................... 319 2 Table 18-10 Characteristics................................................................................................................... 319 Table 18-11. SSI Characteristics .................................................................................................................. 321 Table 18-12. JTAG Characteristics............................................................................................................... 323 Table 18-13. GPIO Characteristics............................................................................................................... 325 Table 18-14. Reset Characteristics .............................................................................................................. 325 July 6, 2006 Preliminary LM3S102 Data Sheet 9 ...
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List of Registers List of Registers System Control ............................................................................................................................... 48 Register 1: Device Identification 0 (DID0), offset 0x000 .............................................................................. 56 Register 2: Device Identification 1 (DID1), offset 0x004 .............................................................................. 57 Register 3: Device Capabilities 0 (DC0), offset 0x008................................................................................. 59 Register ...
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... GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ....................................................... 163 Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038.............................................................. 164 Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ............................................................. 165 Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040................................................ 166 Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044................................................ 167 July 6, 2006 Preliminary LM3S102 Data Sheet 11 ...
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List of Registers Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................... 168 Register 18: GPTM TimerB (GPTMTBR), offset 0x04C .............................................................................. 169 Watchdog Timer............................................................................................................................ 170 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ............................................................................ 173 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ...
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... Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00........................................ 299 Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04.............................................. 300 Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ................................................ 301 Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ............................ 302 July 6, 2006 Preliminary LM3S102 Data Sheet 13 ...
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List of Registers Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ............................................................ 303 Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x24 ............................................................. 304 14 Preliminary July 6, 2006 ...
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... GPTMICR registers from C1bitname and C2bitname to CAbitname and CBbitname • Fixed minor style and edit issues Fourth release of LM3S102 and LM3S102 data sheets. Includes the following changes: • Added initialization and configuration content into PWM, I2C, Comparators, and JTAG chapters. ...
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... About This Document About This Document This data sheet provides reference information for the LM3S102 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers ...
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... Bit cleared chip reset. Bit set chip reset. Nondeterministic. Pin alternate function; a pin defaults to the signal without the brackets. Refers to the physical connection on the package. Refers to the electrical signal encoding of a pin. Preliminary LM3S102 Data Sheet 17 ...
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About This Document Table 1-1. Documentation Conventions Notation assert a signal deassert a signal SIGNAL SIGNAL Numbers Meaning Change the value of the signal from the logically False state to the logically True state. For active High ...
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... These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The LM3S102 controller in the Stellaris family offers the advantages of ARM’s widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the controller uses ARM’ ...
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Architectural Overview • General-purpose timer function with an 8-bit prescaler • Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug – 16-bit Input Capture modes: • Input edge count capture ...
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... Six reset sources – Programmable clock source control – Clock gating to individual peripherals for power savings – IEEE 1149.1-1990 compliant Test Access Port (TAP) controller – Debug access via JTAG and Serial Wire interfaces July 6, 2006 Preliminary LM3S102 Data Sheet 21 ...
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Architectural Overview – Full JTAG boundary scan Industrial-range 28-pin RoHS-compliant SOIC package 1.2 Target Applications Factory automation and control Industrial control power devices Building and home automation Stepper motors 22 Preliminary July 6, 2006 ...
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... Controller (NVIC)) ICode bus LMI JTAG Test Access Port APB Bridge SRAM (TAP) Controller General-Purpose General-Purpose Input/Outputs (GPIOs) Watchdog Universal Asynchronous Receiver/ Transmitter Synchronous (UART) Interface Inter Integrated Circuit (I2C) Comparator Preliminary LM3S102 Data Sheet Flash Timers Timer Serial (SSI) Analog 23 ...
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... Typical applications include switching power supplies and motor control. On the LM3S102, PWM motion control functionality can be achieved through the motion control features of the general-purpose timers (using the CCP pins). The General-Purpose Timer Module’s CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal ...
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... The LM3S102 controller provides one analog comparator that can be configured to drive an output or generate an interrupt. A comparator can compare a test voltage against any one of these voltages: An individual external reference voltage A shared single external reference voltage A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board can be used to signal the application via interrupts to cause it to start capturing a sample sequence ...
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Architectural Overview 2 The I C bus interfaces to external I networking devices, LCDs, tone generators, and so on. The I testing and diagnostic purposes in product development and manufacture. 2 The Stellaris I C module provides the ability to ...
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... Flash (Section 7.2.2 on page 87) The LM3S102 Flash controller supports flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected ...
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Architectural Overview 1.4.7.3 System Control and Clocks (Section 6 on page 48) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection ...
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... System Block Diagram Figure 1-2. LM3S102 Controller System-Level Block Diagram VDD_3.3V LDO GND OSC0 OSC1 RST PA5/SSITx PA4/SSIRx PA3/SSIFss PA2/SSIClk PA1/U0Tx PA0/U0Rx PC3/TDO/SWO PC2/TDI PC1/TMS/SWDIO PC0/TCK/SWCLK LM3S102 July 6, 2006 LDO VDD_2.5V ARM Cortex-M3 (20 MHz) CM3Core DCode ICode NVIC Debug Bus IOSC PLL ...
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ARM Cortex-M3 Processor Core 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational ...
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... Sleep CM3 Core Debug Instructions Data Flash Patch and Breakpoint Private Peripheral Bus (internal ) Adv. High- Perf. Bus Access Port Preliminary LM3S102 Data Sheet ARM Cortex-M3 Output Trace (SWO) Port Interface Unit Peripheral Instrumentation Data Trace Macrocell Watchpoint (external) and Trace Adv ...
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... ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The LM3S102 controller does not include the memory protection unit (MPU) of the ARM Cortex- M3. 2.2.6 Nested Vectored Interrupt Controller (NVIC) 2.2.6.1 Interrupts The ARM® ...
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... Memory Map The memory map for the LM3S102 is provided in Table 3-1. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. ...
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Memory Map Table 3-1. Memory Map (Sheet Start End 0x4002C000 0x4002FFFF 0x40030000 0x40030FFF 0x40031000 0x40031FFF 0x40032000 0x40037FFF 0x40038000 0x4003BFFF 0x4003C000 0x4003CFFF 0x4003D000 0x400FCFFF 0x400FD000 0x400FDFFF 0x400FE000 0x400FFFFF 0x40100000 0x41FFFFFF 0x42000000 0x43FFFFFF 0x44000000 0xDFFFFFFF Private Peripheral Bus 0xE0000000 ...
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... MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed settable Pre fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Preliminary LM3S102 Data Sheet 35 ...
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... System tick timer has fired. This is asynchronous. 16 and settable Asserted from outside the ARM Cortex above fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 lists the interrupts on the LM3S102 controller. Description GPIO Port A GPIO Port B GPIO Port C Reserved UART0 ...
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... Table 4-2. Interrupts (Continued) Interrupt (Bit in Interrupt Registers) 22 23-24 25 26- 30-31 July 6, 2006 Description Timer1b Reserved Analog Comparator 0 Reserved System Control Flash Control Reserved Preliminary LM3S102 Data Sheet 37 ...
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JTAG Interface 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated ...
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... BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 44 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 323 for JTAG timing diagrams. July 6, 2006 Preliminary LM3S102 Data Sheet TDO Cortex-M3 Debug Port ...
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JTAG Interface 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1. Detailed information on each pin follows. Table 5-1. ...
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... TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. July 6, 2006 Preliminary LM3S102 Data Sheet 41 ...
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JTAG Interface Figure 5-2. Test Access Port State Machine Test Logic 1 0 Run Test Idle 0 5.2.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain ...
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... GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. July 6, 2006 Preliminary LM3S102 Data Sheet 43 ...
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JTAG Interface 5.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into ...
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... IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 46 for more information. July 6, 2006 Preliminary LM3S102 Data Sheet 45 ...
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... IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug ...
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... The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. July 6, 2006 GPIO m RST GPIO m+1 Preliminary LM3S102 Data Sheet ... O O TDO GPIO n 47 ...
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System Control 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System ...
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... The BOR circuit has a digital filter that protects against noise-related detection. This feature may be optionally enabled. July 6, 2006 Stellaris RST resistor mitigates any leakage from 2 rapidly when the power supply is turned off Preliminary LM3S102 Data Sheet drops below V . The BTH DD 49 ...
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System Control Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register (see page 65). The BORIOR bit in the PBORCTL register must be set for a brown-out to trigger a reset. The brown-out reset sequence is ...
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... Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC) register (see page 75). Figure 6-2 shows the logic for the main clock tree. The peripheral blocks are driven by the System Clock signal and can be programmatically enabled/disabled. July 6, 2006 Preliminary LM3S102 Data Sheet ). The output may OUT 51 ...
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System Control Figure 6-2. Main Clock Tree OSC1 Main Osc 1-8 MHz OSC2 Internal Osc ÷4 15 MHz a. These are bit fields within the Run-Mode Clock Configuration (RCC) register. 6.1.4.2 PLL Frequency Configuration The user does not have direct ...
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... Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. If the PLL doesn’t lock, the configuration is invalid. 5. Enable use of the PLL by clearing the BYPASS bit in RCC. Important: If the BYPASS bit is cleared before the PLL locks possible to render the device unusable. July 6, 2006 Preliminary LM3S102 Data Sheet 53 ...
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System Control 6.3 Register Map Table 6-1 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register’s address, relative to the System Control base address of 0x400FE000. Table 6-1. System Control Register ...
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... Sleep-Mode Clock Gating Control 0 R/W Sleep-Mode Clock Gating Control 1 R/W Sleep-Mode Clock Gating Control 2 R/W Deep-Sleep-Mode Clock Gating Control 0 R/W Deep-Sleep-Mode Clock Gating Control 1 R/W Deep-Sleep-Mode Clock Gating Control 2 R/W Clock verification clear R/W Allow unregulated LDO to reset the part Preliminary LM3S102 Data Sheet See page ...
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System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Offset 0x000 reserved VER Type Reset ...
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... The 0x0 value indicates the Stellaris family of microcontrollers. RO 0x02 Part Number This field provides the part number of the device within the family. The 0x02 value indicates the LM3S102 microcontroller Reserved bits return an indeterminate value, and should never be changed. RO see table Temperature Range This field specifies the temperature rating of the device ...
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System Control Bit/Field Name Type 2 RoHS 1:0 QUAL 58 Reset Description RO 1 RoHS-Compliance this bit specifies the device is RoHS-compliant. RO see table This field specifies the qualification status of the device. This field is ...
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... Reset Description RO 0x0007 Indicates the size of the on-chip SRAM. A value of 0x0007 indicates SRAM. RO 0x0003 Indicates the size of the on-chip flash memory. A value of 0x03 indicates Flash. Preliminary LM3S102 Data Sheet ...
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System Control Register 4: Device Capabilities 1 (DC1), offset 0x010 This register is predefined by the part and can be used to verify features. Device Capabilities 1 (DC1) Offset 0x010 Type Reset ...
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... Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) register (see page 113). Bits that are not noted are passed as 0. July 6, 2006 Type Reset Description this bit indicates the presence of the ARM Serial Wire Debug (SWD) capabilities this bit indicates the presence of a JTAG port. Preliminary LM3S102 Data Sheet 61 ...
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System Control Register 5: Device Capabilities 2 (DC2), offset 0x014 This register is predefined by the part and can be used to verify features. Device Capabilities 2 (DC2) Offset 0x014 reserved Type ...
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... this bit indicates the presence of the C0o pin this bit indicates the presence of the C0+ pin this bit indicates the presence of the C0- pin Reserved bits return an indeterminate value, and should never be changed. Preliminary LM3S102 Data Sheet reserved ...
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System Control Register 7: Device Capabilities 4 (DC4), offset 0x01C This register is predefined by the part and can be used to verify features. Device Capabilities 4 (DC4) Offset 0x01C Type Reset ...
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... BOR condition interrupt or reset. If the BOR resample is deasserted, the cause of the initial assertion was likely noise and the interrupt or reset is suppressed. If BORWT is 0, BOR assertions do not resample the output and any condition is reported immediately if enabled. Preliminary LM3S102 Data Sheet ...
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System Control Register 9: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (V LDO Power Control (LDOPCTL) Offset 0x034 Type Reset 0 0 ...
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... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. 0 Reset control for the Watchdog unit Reserved bits return an indeterminate value, and should never be changed. Preliminary LM3S102 Data Sheet R ...
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System Control Register 11: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register (see page 62). Software Reset Control 1 (SRCR1) Offset 0x044 ...
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... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. 0 Reset control for GPIO Port C. 0 Reset control for GPIO Port B. 0 Reset control for GPIO Port A. Preliminary LM3S102 Data Sheet ...
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System Control Register 13: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Offset 0x050 Type Reset ...
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... MOFRIS is set; otherwise, an interrupt is not generated. 0 LDO Power Unregulated Interrupt Mask This bit specifies whether an LDO unregulated power situation is promoted to a controller interrupt. If set, an interrupt is generated if LDORIS is set; otherwise, an interrupt is not generated. Preliminary LM3S102 Data Sheet ...
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System Control Bit/Field Name Type 1 BORIM R/W 0 PLLFIM R/W 72 Reset Description 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS ...
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... BORIOR bit in the PBORCTL register is cleared. The interrupt is cleared by writing this bit. 0 PLL Fault Masked Interrupt Status This bit is set if a PLL fault is detected (stops oscillating). The interrupt is cleared by writing this bit. Preliminary LM3S102 Data Sheet ...
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System Control Register 16: Reset Cause (RESC), offset 0x05C This field specifies the cause of the reset event to software. The reset value is determined by the cause of the reset. When an external reset is the cause (EXT is ...
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... The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller sleep mode and the peripheral is unused. Preliminary LM3S102 Data Sheet reserved ...
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System Control Bit/Field Name 26:23 SYSDIV 22 USESYSDIV 21:14 reserved 13 PWRDN 12 OEN 11 BYPASS 76 Type Reset Description R/W 0xF System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output (200 ...
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... Reserved bits return an indeterminate value, and should never be changed. OEN Mode X Power down 0 Normal Crystal Frequency (MHz) reserved 3.579545 MHz 3.6864 MHz Preliminary LM3S102 Data Sheet Input Source Main oscillator (default) Internal oscillator Internal oscillator / 4 (this is necessary if used as input to PLL) reserved 77 ...
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System Control Table 6-4. Default Crystal Field Values and PLL Programming (Continued) Crystal Number (XTAL Binary Value) 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 78 Crystal Frequency (MHz) 4 MHz 4.096 MHz 4.9152 MHz 5 MHz 5.12 ...
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... RO - This field specifies the value supplied to the PLL’s OD input This field specifies the value supplied to the PLL’s F input This field specifies the value supplied to the PLL’s R input. Preliminary LM3S102 Data Sheet ...
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System Control Register 19: Run-Mode Clock Gating Control 0 (RCGC0), offset 0x100 Register 20: Sleep-Mode Clock Gating Control 0 (SCGC0), offset 0x110 Register 21: Deep-Sleep-Mode Clock Gating Control 0 (DCGC0), offset 0x120 These registers control the clock gating logic. Each ...
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... This bit controls the clock gating for the General Purpose Timer 0 module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled Reserved bits return an indeterminate value, and should never be changed. Preliminary LM3S102 Data Sheet reserved GPTM1 GPTM0 ...
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System Control Bit/Field Name Type 12 I2C R/W 11:5 reserved 4 SSI R/W 3:1 reserved 0 UART0 R/W 82 Reset Description 0 This bit controls the clock gating for the I the unit receives a clock and functions. Otherwise, the ...
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... If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 0 This bit controls the clock gating for the GPIO Port A module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. Preliminary LM3S102 Data Sheet ...
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System Control Register 28: Clock Verification Clear (CLKVCLR), offset 0x150 This register is provided as a means of clearing the clock verification circuits by software. Since the clock verification circuits force a known good clock to control the process, the ...
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... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. 0 Set allow unregulated LDO output to reset the part. Preliminary LM3S102 Data Sheet ...
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... Internal Memory 7 Internal Memory The LM3S102 microcontroller comes with bit-banded SRAM and flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1. Flash Block Diagram ...
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... Flash Memory Protection Read Enable (FMPRE): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed. The contents of the memory block are prohibited from being accessed as data and traversing the DCode bus. July 6, 2006 Preliminary LM3S102 Data Sheet 87 ...
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Internal Memory The policies may be combined as shown in Table 7-1. Table 7-1. Flash Protection Policy Combinations FMPPE FMPRE access that attempts to program or erase a PE-protected block is ...
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... Flash memory program protect 0x13 R/W USec reload R/W Flash memory address R/W Flash memory data R/W Flash memory control RO Flash controller raw interrupt status R/W Flash controller interrupt mask R/W1C Flash controller masked interrupt status and clear Preliminary LM3S102 Data Sheet See page ...
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Internal Memory 7.5 Register Descriptions The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. 90 Preliminary July 6, 2006 ...
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... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. R/W0 0x0F Enable 2-KB flash blocks to be written or erased (FMPPE register), or executed or read (FMPRE register). The policies may be combined as shown in Table 7-1 on page 88. Preliminary LM3S102 Data Sheet ...
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Internal Memory Register 3: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400FE000 This register is provided as a means of creating a 1 μs tick divider reload value for the flash controller. ...
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... R/W R/W R/W R/W R/W R Reset Description RO 0x0 Reserved bits return an indeterminate value, and should never be changed. 0x0 Address offset in flash where operation is performed. Preliminary LM3S102 Data Sheet OFFSET R/W R/W R/W R/W R/W 0 ...
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Internal Memory Register 5: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read ...
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... A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete returned; otherwise, if the previous mass erase access is not complete returned. This can take up to 250 ms. Preliminary LM3S102 Data Sheet ...
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Internal Memory Bit/Field Name Type 1 ERASE R/W 0 WRITE R/W 96 Reset Description 0 Erase a page of flash memory If this bit is set, the page of flash main memory as specified by the contents of FMA is ...
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... Flash Memory Protection Read Enable (FMPRE) and Flash Memory Protection Program Enable (FMPPE) registers (see page 91). Otherwise, no access has tried to improperly access the flash. Preliminary LM3S102 Data Sheet ...
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Internal Memory Register 8: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Offset 0x010 Type Reset ...
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... This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. Preliminary LM3S102 Data Sheet ...
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General-Purpose Input/Outputs (GPIOs) 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of three physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, and Port C). The GPIO module is FiRM-compliant and supports up to ...
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... JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR external reset (RST) puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-2). The LM3S102 microcontroller contains three ports and thus three of these physical GPIO blocks. July 6, 2006 U0Rx ...
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General-Purpose Input/Outputs (GPIOs) Figure 8-2. GPIO Port Block Diagram Function Selection GPIOAFSEL Alternate Input Alternate Output Alternate Output Enable GPIO Input I/O Data GPIO Output GPIODATA GPIO Output Enable GPIODIR Interrupt Control GPIOIS GPIOIBE Interrupt GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR ...
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... ADDR[9: 0x0C4 GPIODATA Returned Value Preliminary LM3S102 Data Sheet 103 ...
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General-Purpose Input/Outputs (GPIOs) Interrupts are cleared by writing the GPIO Interrupt Clear (GPIOICR) register (see page 116). When programming interrupts, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register ...
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... Register Bit Value Pin 2 Bit Value Preliminary LM3S102 Data Sheet ...
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General-Purpose Input/Outputs (GPIOs) 8.4 Register Map Table 8-2 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: GPIO Port A: 0x40004000 GPIO Port B: 0x40005000 GPIO Port ...
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... Peripheral identification 0 RO Peripheral identification 1 RO Peripheral identification 2 RO Peripheral identification 3 RO GPIO PrimeCell identification 0 RO GPIO PrimeCell identification 1 RO GPIO PrimeCell identification 2 RO GPIO PrimeCell identification 3 Preliminary LM3S102 Data Sheet See page 129 130 131 132 133 134 135 136 137 107 ...
Page 108
General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been ...
Page 109
... R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Data Direction 0: Pins are inputs. 1: Pins are outputs. Preliminary LM3S102 Data Sheet DIR ...
Page 110
General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins ...
Page 111
... GPIO Interrupt Both Edges 0: Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 142). 1: Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. Preliminary LM3S102 Data Sheet ...
Page 112
General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding ...
Page 113
... RO RO R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Interrupt Mask Enable 0: Corresponding pin interrupt is masked. 1: Corresponding pin interrupt is not masked. Preliminary LM3S102 Data Sheet ...
Page 114
General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that ...
Page 115
... Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. 0: Corresponding GPIO line interrupt not active. 1: Corresponding GPIO line asserting interrupt. Preliminary LM3S102 Data Sheet ...
Page 116
General-Purpose Input/Outputs (GPIOs) Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has ...
Page 117
... GPIO pins, with the exception of the five JTAG pins ( default to JTAG functionality. Because of this, the default reset value of GPIOAFSEL for GPIO Port B is 0x80 while the default reset value of GPIOAFSEL for Port C is 0x0F. Preliminary LM3S102 Data Sheet ...
Page 118
General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When ...
Page 119
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 Output Pad 4-mA Drive Enable A write either corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. Preliminary LM3S102 Data Sheet ...
Page 120
General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When ...
Page 121
... RO RO R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 Output Pad Open Drain Enable 0: Open drain configuration is disabled. 1: Open drain configuration is enabled. Preliminary LM3S102 Data Sheet ...
Page 122
General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit ...
Page 123
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 Pad Weak Pull-Down Enable GPIOPUR A write GPIOPDR [n] enables. The change is effective on the second clock cycle after the write. Preliminary LM3S102 Data Sheet ...
Page 124
General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive ...
Page 125
... R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0xFF Digital-Input Enable 0: Digital input disabled 1: Digital input enabled Preliminary LM3S102 Data Sheet DEN R/W ...
Page 126
General-Purpose Input/Outputs (GPIOs) Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to ...
Page 127
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. RO 0x00 GPIO Peripheral ID Register[15:8] Preliminary LM3S102 Data Sheet PID5 ...
Page 128
General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to ...
Page 129
... Reset Description RO 0 Reserved bits return an indeterminate value, and should never be changed. RO 0x00 GPIO Peripheral ID Register[31:24] Preliminary LM3S102 Data Sheet PID7 ...
Page 130
General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to ...
Page 131
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. Preliminary LM3S102 Data Sheet ...
Page 132
General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to ...
Page 133
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x01 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. Preliminary LM3S102 Data Sheet ...
Page 134
General-Purpose Input/Outputs (GPIOs) Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard ...
Page 135
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0xF0 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. Preliminary LM3S102 Data Sheet ...
Page 136
General-Purpose Input/Outputs (GPIOs) Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard ...
Page 137
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0xB1 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. Preliminary LM3S102 Data Sheet ...
Page 138
... General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The LM3S102 controller General-Purpose Timer Module (GPTM) contains two GPTM blocks (Timer0 and Timer1). Each GPTM block provides two 16-bit timer/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC) ...
Page 139
... July 6, 2006 0x0000 (Down Counter Modes ) GPTMTAPMR TA Comparator GPTMTAPR GPTMTAILR GPTMAR GPTMTAMR GPTMTBR GPTMTBPMR GPTMTBPR TB Comparator GPTMTBILR GPTMTBMR 0x0000 (Down Counter Modes ) Preliminary LM3S102 Data Sheet Clock / Edge Detect En RTC Divider En Clock / Edge Detect 32KHz CCP1 139 ...
Page 140
General-Purpose Timers 9.2.2 32-Bit Timer Operating Modes Note: The odd-numbered CCP pins are used for 16-bit input and the even-numbered CCP pins are used for 32-bit input. This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) ...
Page 141
... If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). July 6, 2006 Preliminary LM3S102 Data Sheet 141 ...
Page 142
General-Purpose Timers Table 9-1. 16-Bit Timer With Prescaler Configurations Prescale 00000000 00000001 00000010 ------------ 11111100 11111110 11111111 the clock period. C 9.2.3.2 16-Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a ...
Page 143
... Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). July 6, 2006 Timer reload on next cycle Preliminary LM3S102 Data Sheet Ignored Ignored Timer stops, flags asserted 143 ...
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General-Purpose Timers Figure 9-3. 16-Bit Input Edge Time Mode Example Count 0xFFFF Input Signal 9.2.3.4 16-Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with ...
Page 145
... Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). July 6, 2006 GPTMTnR=GPTMnMR TnEN set Preliminary LM3S102 Data Sheet GPTMTnR=GPTMnMR Time 145 ...
Page 146
General-Purpose Timers In One-Shot mode, the timer stops counting after step 7. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.2 32-Bit Real-Time Clock (RTC) Mode To ...
Page 147
... Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. July 6, 2006 Preliminary LM3S102 Data Sheet 147 ...
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General-Purpose Timers prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register and the GPTM Timern Prescale Match (GPTMTnPMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the ...
Page 149
... The default reset value for the GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers is 0x0000FFFF when in 16-bit mode and 0xFFFFFFFF when in 32-bit mode. 9.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. July 6, 2006 Reset Type Description a RO TimerA RO TimerB Preliminary LM3S102 Data Sheet See page 168 169 149 ...
Page 150
General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Offset 0x000 ...
Page 151
... The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. Preliminary LM3S102 Data Sheet ...
Page 152
General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, ...
Page 153
... TimerB stalling is disabled. 1: TimerB stalling is enabled. 0 GPTM TimerB Enable 0: TimerB is disabled. 1: TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 0 Reserved bits return an indeterminate value, and should never be changed. Preliminary LM3S102 Data Sheet ...
Page 154
General-Purpose Timers Bit Name Type 6 TAPWML R/W 5 TAOTE R/W 4 RTCEN R/W 3:2 TAEVENT R/W 1 TASTALL R/W 0 TAEN R/W 154 Reset Description 0 GPTM TimerA PWM Output Level 0: Output is unaffected. 1: Output is inverted. ...
Page 155
... GPTM TimerB Time-Out Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 0 Reserved bits return an indeterminate value, and should never be changed. 0 GPTM RTC Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 0 GPTM CaptureA Event Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. Preliminary LM3S102 Data Sheet ...
Page 156
General-Purpose Timers Bit Name Type 1 CAMIM R/W 0 TATOIM R/W 156 Reset Description 0 GPTM CaptureA Match Interrupt Mask 0: Interrupt is disabled. 1: Interrupt is enabled. 0 GPTM TimerA Time-Out Interrupt Mask 0: Interrupt is disabled. 1: Interrupt ...
Page 157
... This is the CaptureA Event interrupt status prior to masking. 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. Preliminary LM3S102 Data Sheet ...
Page 158
General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, ...
Page 159
... GPTM CaptureA Event Interrupt Clear 0: The interrupt is unaffected. 1: The interrupt is cleared. 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking. 0 GPTM TimerA Time-Out Raw Interrupt 0: The interrupt is unaffected. 1: The interrupt is cleared. Preliminary LM3S102 Data Sheet ...
Page 160
General-Purpose Timers Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register ...
Page 161
... Reserved bits return an indeterminate value, and should never be changed. 0xFFFF GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. Preliminary LM3S102 Data Sheet ...
Page 162
General-Purpose Timers Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Offset 0x030 Type R/W R/W ...
Page 163
... GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. Preliminary LM3S102 Data Sheet ...
Page 164
General-Purpose Timers Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers. GPTM TimerA Prescale (GPTMTAPR) Offset 0x038 Type Reset 0 0 ...
Page 165
... Reserved bits return an indeterminate value, and should never be changed. 0 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-1 on page 142 for more details and an example. Preliminary LM3S102 Data Sheet ...
Page 166
General-Purpose Timers Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits. GPTM TimerA Prescale Match (GPTMTAPMR) Offset 0x040 Type Reset 0 ...
Page 167
... R/W R Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0 GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. Preliminary LM3S102 Data Sheet ...
Page 168
General-Purpose Timers Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the ...
Page 169
... Reserved bits return an indeterminate value, and should never be changed. 0xFFFF GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. Preliminary LM3S102 Data Sheet ...
Page 170
Watchdog Timer 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error ...
Page 171
... Watchdog Timer base address of 0x40000000. Table 10-1. WDT Register Map Offset Name 0x000 WDTLOAD 0xFFFFFFFF 0x004 WDTVALUE 0xFFFFFFFF 0x008 WDTCTL 0x00000000 July 6, 2006 WatchdogResetEnable Reset Type Description R/W Load RO Current value R/W Control Preliminary LM3S102 Data Sheet function), the Watchdog timer See page 173 174 175 171 ...
Page 172
Watchdog Timer Table 10-1. WDT Register Map (Continued) Offset Name 0x00C WDTICR 0x010 WDTRIS 0x00000000 0x014 WDTMIS 0x00000000 0x418 WDTTEST 0x00000000 0xC00 WDTLOCK 0x00000000 0xFD0 WDTPeriphID4 0x00000000 0xFD4 WDTPeriphID5 0x00000000 0xFD8 WDTPeriphID6 0x00000000 0xFDC WDTPeriphID7 0x00000000 0xFE0 WDTPeriphID0 0x00000005 0xFE4 ...
Page 173
... Name Type 31:0 WDTLoad R/W July 6, 2006 WDTLoad R/W R/W R/W R/W R/W R WDTLoad R/W R/W R/W R/W R/W R Reset Description 0xFFFFFFFF Watchdog Load Value Preliminary LM3S102 Data Sheet R/W R/W R/W R/W R R/W R/W R/W R 173 ...
Page 174
Watchdog Timer Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Offset 0x004 Type Reset ...
Page 175
... Watchdog Reset Enable 0: Disabled. 1: Enable the Watchdog module reset output. 0 Watchdog Interrupt Enable 0: Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset) 1: Interrupt event enabled. Once enabled, all writes are ignored. Preliminary LM3S102 Data Sheet ...
Page 176
Watchdog Timer Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for ...
Page 177
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. Preliminary LM3S102 Data Sheet ...
Page 178
Watchdog Timer Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog ...
Page 179
... Watchdog Lock A write of the value 0x1ACCE551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Locked: 0x00000001 Unlocked: 0x00000000 Preliminary LM3S102 Data Sheet R/W ...
Page 180
Watchdog Timer Register 8: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Offset 0x418 Type Reset 0 ...
Page 181
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 WDT Peripheral ID Register[7:0] Preliminary LM3S102 Data Sheet PID4 ...
Page 182
Watchdog Timer Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Offset 0xFD4 Type RO RO ...
Page 183
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x00 WDT Peripheral ID Register[23:16] Preliminary LM3S102 Data Sheet PID6 ...
Page 184
Watchdog Timer Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Offset 0xFDC Type RO RO ...
Page 185
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x05 Watchdog Peripheral ID Register[7:0] Preliminary LM3S102 Data Sheet PID0 ...
Page 186
Watchdog Timer Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Offset 0xFE4 Type RO RO ...
Page 187
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x18 Watchdog Peripheral ID Register[23:16] Preliminary LM3S102 Data Sheet PID2 ...
Page 188
Watchdog Timer Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Offset 0xFEC Type RO RO ...
Page 189
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x0D Watchdog PrimeCell ID Register[7:0] Preliminary LM3S102 Data Sheet CID0 ...
Page 190
Watchdog Timer Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 1 (WDTPCellID1) Offset 0xFF4 Type RO RO ...
Page 191
... Reset Description 0 Reserved bits return an indeterminate value, and should never be changed. 0x05 Watchdog PrimeCell ID Register[23:16] Preliminary LM3S102 Data Sheet CID2 ...
Page 192
Watchdog Timer Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Primecell Identification 3 (WDTPCellID3) Offset 0xFFC Type RO ...
Page 193
... Universal Asynchronous Receiver/Transmitter (UART) The Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550-type serial interface characteristics. The LM3S102 controller is equipped with one UART module. The UART has the following features: Separate transmit and receive FIFOs Programmable FIFO length, including 1-byte deep operation providing conventional ...
Page 194
Universal Asynchronous Receiver/Transmitter (UART) 11.1 Block Diagram Figure 11-1. UART Module Block Diagram System Clock Interrupt Control Interrupt Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 Control / Status UARTPeriphID5 UARTRSR/ECR UARTPeriphID6 UARTPeriphID7 11.2 Functional Description ...
Page 195
... UARTIBRD write, UARTFBRD write, and UARTLCRH write UARTFBRD write, UARTIBRD write, and UARTLCRH write UARTIBRD write and UARTLCRH write UARTFBRD write and UARTLCRH write July 6, 2006 UnTX LSB MSB 1 5-8 data bits 0 n Parity bit if enabled Start Preliminary LM3S102 Data Sheet 1-2 stop bits 195 ...
Page 196
Universal Asynchronous Receiver/Transmitter (UART) 11.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. ...
Page 197
... UARTFBRD[DIVFRAC] = integer(0.8507 * With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. July 6, 2006 Preliminary LM3S102 Data Sheet 197 ...
Page 198
Universal Asynchronous Receiver/Transmitter (UART) 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x00000060). 5. Enable the UART by setting the ...
Page 199
... The remainder of this section lists and describes the UART registers, in numerical order by address offset. July 6, 2006 Reset Type Description RO PrimeCell identification 0 RO PrimeCell identification 1 RO PrimeCell identification 2 RO PrimeCell identification 3 Preliminary LM3S102 Data Sheet See page 225 226 227 228 199 ...
Page 200
Universal Asynchronous Receiver/Transmitter (UART) Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are ...