LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 158

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Timers
158
Reset
Reset
Type
Type
GPTM Masked Interrupt Status (GPTMMIS)
Offset 0x020
31:11
RO
RO
31
15
0
0
7:4
Bit
10
9
8
3
2
1
0
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
RO
RO
30
14
0
0
TBTOMIS
TATOMIS
CBMMIS
CAMMIS
reserved
CBEMIS
reserved
RTCMIS
CAEMIS
Name
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
CBEMIS
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
0
CBMMIS TBTOMIS
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM CaptureB Event Masked Interrupt
This is the CaptureB event interrupt status after masking.
GPTM CaptureB Match Masked Interrupt
This is the CaptureB match interrupt status after masking.
GPTM TimerB Time-Out Masked Interrupt
This is the TimerB time-out interrupt status after masking.
Reserved bits return an indeterminate value, and should never
be changed.
GPTM RTC Masked Interrupt
This is the RTC event interrupt status after masking.
GPTM CaptureA Event Masked Interrupt
This is the CaptureA event interrupt status after masking.
GPTM CaptureA Match Masked Interrupt
This is the CaptureA match interrupt status after masking.
GPTM TimerA Time-Out Masked Interrupt
This is the TimerA time-out interrupt status after masking.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RTCMIS CAEMIS CAMMIS TATOMIS
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
July 6, 2006
0
1
0
RO
RO
16
0
0
0