LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 239

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

12.4
Table 12-1. SSI Register Map
12.5
July 6, 2006
0xFDC
0xFEC
Offset
0x00C
0x01C
0xFD0
0xFD4
0xFD8
0xFE0
0xFE4
0xFE8
0xFFC
0xFF0
0xFF4
0xFF8
0x000
0x004
0x008
0x010
0x014
0x018
0x020
SSIPeriphID4
SSIPeriphID5
SSIPeriphID6
SSIPCellID3
Name
SSICR0
SSICR1
SSIDR
SSISR
SSICPSR
SSIIM
SSIRIS
SSIMIS
SSIICR
SSIPeriphID7
SSIPeriphID0
SSIPeriphID1
SSIPeriphID2
SSIPeriphID3
SSIPCellID0
SSIPCellID1
SSIPCellID2
4.
5.
Register Map
Table 12-1 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the SSI base address of 0x40008000.
Note:
Register Descriptions
The remainder of this section lists and describes the SSI registers, in numerical order by address
offset.
Write the SSICR0 register with a value of 0x000009C7.
The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the
control registers are reprogrammed.
0x0000000D
0x00000000
0x00000000
0x00000000
0x00000003
0x00000000
0x00000000
0x00000008
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000022
0x00000000
0x00000018
0x000000F0
0x00000005
0x000000B1
0x00000001
Reset
Type
W1C
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Preliminary
Description
Control 0
Control 1
Data
Status
Clock prescale
Interrupt mask
Raw interrupt status
Masked interrupt status
Interrupt clear
Peripheral identification 4
Peripheral identification 5
Peripheral identification 6
Peripheral identification 7
Peripheral identification 0
Peripheral identification 1
Peripheral identification 2
Peripheral identification 3
PrimeCell identification 0
PrimeCell identification 1
PrimeCell identification 2
PrimeCell identification 3
LM3S102 Data Sheet
page
See
240
242
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
239