LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 233

• Manufacturer Part Number: LM3S102
• Description: Lm3s102 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

12.2.4.4
July 6, 2006
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0
In this configuration, during idle periods:
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. This causes slave data to be enabled
onto the SSIRx input line of the master. The master SSITx output pad is enabled.
One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the
master and slave data have been set, the SSIClk master clock pin goes High after one further
half SSIClk period.
The data is now captured on the rising and propagated on the falling edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the
SSIFss line is returned to its idle High state one SSIClk period after the last bit has been
captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be
pulsed High between each data word transfer. This is because the slave select pin freezes the
data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero.
Therefore, the master device must raise the SSIFss pin of the slave device between each data
transfer to enable the serial peripheral data write. On completion of the continuous transfer, the
SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured.
Freescale SPI Frame Format with SPO=0 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in
Figure 12-6, which covers both single and continuous transfers.
SSIClk
SSIFss
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
When the SSI is configured as a master, it enables the SSIClk pad
When the SSI is configured as a slave, it disables the SSIClk pad
SSITx
SSIRx
SSIClk
SSIFss
SSIRx
SSITx
LSB
LSB
MSB
MSB
MSB
MSB
Preliminary
4 to 16 bits
4 to 16 bits
LSB
LSB
LM3S102 Data Sheet
MSB
MSB
LSB
LSB
Q
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