MT16LSDT1664 Micron, MT16LSDT1664 Datasheet - Page 3

• Manufacturer Part Number: MT16LSDT1664
• Description: 168-Pin SDRAM DIMMs (x64)
• Manufacturer: Micron

PIN DESCRIPTIONS
NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment tables for pin number and symbol information.
8, 16 Meg x 64 SDRAM DIMMs
SD8_16C8_16X64AG_A.p65 – Rev. A, Pub. 4/02
117, 118, 119, 120, 121,
33, 34, 35, 36, 37, 38,
112, 113, 130, 131
PIN NUMBERS
42, 79, 125, 163
30, 45, 114, 129
28, 29, 46, 47,
27, 111, 115
63, 128
39, 122
123
83
DQMB0-DQMB7
RAS#, CAS#,
CKE0, CKE1
SYMBOL
BA0, BA1
CK0-CK3
S0#-S3#
A0-A11
WE#
SCL
Input
TYPE
Input
Input
Input
Input
Input
Input
Input
3
Command Inputs: RAS#, CAS#, and WE# (along with
S#) define the command being entered.
Clock: CK is driven by the system clock. All SDRAM
input signals are sampled on the positive edge of CK.
CK also increments the internal burst counter and
controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates
(LOW) the CK signal. Deactivating the clock provides
PRECHARGE POWER-DOWN and SELF REFRESH
operation (all device banks idle), ACTIVE POWER-
DOWN (row ACTIVE in any device bank) or CLOCK
SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-
down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The
input buffers, including CK, are disabled during
power-down and self refresh modes, providing low
standby power.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All com-
mands are masked when S# is registered HIGH. S# is
considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for
write accesses and an output enable signal for read
accesses. Input data is masked when DQMB is sampled
HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when
DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which device
bank the ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column addres and auto
precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the
respective device bank. A10 sampled during a
PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW,
device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address input also provide the
op-code during a MODE REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM DIMMs
DESCRIPTION
64MB / 128MB (x64)
©2002, Micron Technology, Inc.