MT16LSDT1664 Micron, MT16LSDT1664 Datasheet - Page 9

• Manufacturer Part Number: MT16LSDT1664
• Description: 168-Pin SDRAM DIMMs (x64)
• Manufacturer: Micron

are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached, as shown in the Burst Defini-
tion Table. The block is uniquely selected by A1–A8
when the burst length is set to two; by A2–A8 when the
burst length is set to four; and by A3–A8 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. Full-page bursts wrap within the
page if the boundary is reached, as shown in the Burst
Definition Table.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in the Burst Definition
Table.
8, 16 Meg x 64 SDRAM DIMMs
SD8_16C8_16X64AG_A.p65 – Rev. A, Pub. 4/02
COMMAND
COMMAND
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
CLK
CLK
DQ
DQ
READ
READ
T0
T0
CAS Latency = 2
CAS Latency
Diagram
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
9
CAS Latency
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in the CAS Latency Diagram. The CAS Latency
Table indicates the operating frequencies at which each
CAS latency setting can be used.
operation or incompatibility with future versions may
result.
Operating Mode
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
SPEED
-13E
-133
-10E
The CAS latency is the delay, in clock cycles, be-
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by setting
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via M0-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LATENCY = 2
168-PIN SDRAM DIMMs
CLOCK FREQUENCY (MHz)
ALLOWABLE OPERATING
≤ 133
≤ 100
≤ 100
CAS
CAS Latency
64MB / 128MB (x64)
Table
LATENCY = 3
©2002, Micron Technology, Inc.
≤ 143
≤ 133
CAS
NA