MT16LSDT1664 Micron, MT16LSDT1664 Datasheet - Page 7

• Manufacturer Part Number: MT16LSDT1664
• Description: 168-Pin SDRAM DIMMs (x64)
• Manufacturer: Micron

GENERAL DESCRIPTION
speed CMOS, dynamic random-access 64MB and
128MB unbuffered memory modules, organized in x64
configurations. These modules use internally config-
ured quad-bank SDRAMs with a synchronous inter-
face (all signals are registered on the positive edge of
the clock signal CK). The four banks of the x8 config-
ured SDRAM devices, used for these modules, are con-
figured as 4,096 bit-rows by 512 bit-columns, by 8 in-
put/output bits.
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the device bank and row to be accessed (BA0,
BA1 select the device bank, A0-A11 select the device
row). The address bits A0–A8 registered coincident
with the READ or WRITE command are used to select
the starting column location for the burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one device bank while
accessing one of the other three device banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access. For
more information regarding SDRAM operation, refer to
the 64Mb SDRAM data sheet.
8, 16 Meg x 64 SDRAM DIMMs
SD8_16C8_16X64AG_A.p65 – Rev. A, Pub. 4/02
The MT8LSDT864A and MT16LSDT1664A are high-
Read and write accesses to the SDRAM modules are
These modules provide for programmable READ or
These modules use an internal pipelined architec-
These modules are designed to operate in 3.3V, low-
SDRAM modules offer substantial advances in
7
Serial Presence Detect Operation
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Mi-
cron to identify the module type, SDRAM characteristics
and module timing parameters. The remaining 128
bytes of storage are available for use by the customer.
System READ/WRITE operations between the master
(system logic) and the slave EEPROM device (DIMM)
occur via a standard IIC bus using the DIMM’s SCL (clock)
and SDA (data) signals, together with SA(2:0), which
provide eight unique DIMM/EEPROM addresses.
REGISTER DEFINITION
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions, and device operation.
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this
100µs period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
least one COMMAND INHIBIT or NOP command hav-
ing been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Mode Register
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode, and a write burst mode, as
shown in the Mode Register Definition Diagram.
The mode register is programmed via the LOAD MODE
These modules incorporate serial presence-detect
Prior to normal operation, the SDRAM must be ini-
SDRAMs must be powered up and initialized in a
Once the 100µs delay has been satisfied with at
Once in the idle state, two AUTO REFRESH cycles
The mode register is used to define the specific mode
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM DIMMs
64MB / 128MB (x64)
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and V
©2002, Micron Technology, Inc.
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