MT16LSDT1664 Micron, MT16LSDT1664 Datasheet - Page 8

• Manufacturer Part Number: MT16LSDT1664
• Description: 168-Pin SDRAM DIMMs (x64)
• Manufacturer: Micron

REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses
power.
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
8, 16 Meg x 64 SDRAM DIMMs
SD8_16C8_16X64AG_A.p65 – Rev. A, Pub. 4/02
to ensure compatibility
with future devices.
M11, M10 = “0, 0”
*Should program
Mode register bits M0–M2 specify the burst length,
The mode register must be loaded when all device
Reserved* WB
11
A11
Mode Register Definition
10
A10
M9
0
1
9
A9
Op Mode
8
A8
7
A7
Diagram
Programmed Burst Length
M8
0
-
Single Location Access
CAS Latency
6
Write Burst Mode
A6
5
M7
A5
0
-
4
A4
BT
M3
Defined
0
1
M6-M0
3
A3
-
M6
M2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Burst Length
2
M1
M5
A2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Burst Type
Interleaved
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8
8
Violating either of these requirements will result in
unspecified operation.
Burst Length
oriented, with the burst length being programmable,
as shown in Mode Register Definition Diagram. The
burst length determines the maximum number of col-
umn locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations
NOTE: 1. For full-page accesses: y = 512.
Length
Burst
Page
Full
Read and write accesses to the SDRAM are burst
(y)
2
4
8
2. For a burst length of two, A1-A8 select the block-
3. For a burst length of four, A2-A8 select the block-
4. For a burst length of eight, A3-A8 select the block-
5. For a full-page burst, the full row is selected and
6. Whenever a boundary of the block is reached
7. For a burst length of one, A0-A8 select the unique
Starting Column
of-two burst; A0 selects the starting column
within the block.
of-four burst; A0-A1 select the starting column
within the block.
of-eight burst; A0-A2 select the starting column
within the block.
A0-A8 select the starting column.
within a given sequence above, the following
access wraps within the block.
column to be accessed, and mode register bit M3
is ignored.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A2 A1 A0
(location 0-y)
0
0
0
0
1
1
1
1
n = A0-A8
Address:
A1 A0
168-PIN SDRAM DIMMs
0
0
1
1
0
0
1
1
0
0
1
1
Burst Definition
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64MB / 128MB (x64)
Type = Sequential Type = Interleaved
Cn, Cn + 1, Cn + 2
Table
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Order of Accesses Within a Burst
…Cn - 1,
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn…
0-1
1-0
©2002, Micron Technology, Inc.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0