cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet
cy27ee16
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cy27ee16 Summary of contents
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... C Serial Familiar industry standard eases programming effort and enables update of data stored in 16K EEPROM scratchpad and 2K EEPROM clock control block while CY27EE16ZE is installed in system. Meets critical timing requirements in complex system designs. Write Protect (WP pin) can be programmed to serve as an analog control voltage for a VCXO ...
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... Fractional N and frequency select pins (FS) are programmable; contact factory for details. Write Protect (WP) – Active HIGH The default clock configuration of the CY27EE16ZE has pin 17 configured as WP. When a logical HIGH level input is asserted on this pin, the write protect feature (WP) will inhibit writing to the EEPROM ...
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... Power-down Mode (PDM) – Active LOW The Power-down Mode (PDM) function is available when pin 10 of the CY27EE16ZE is configured as PDM. When the PDM signal pulled LOW, all clock components are shut down and the part enters a low-power state. To configure pin 10 of the CY27EE16ZE as PDM, see " ...
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... CLK = REF/Post Divider CLK = REF The basic PLL block diagram is shown in Figure 2. Each of the six clock outputs on the CY27EE16ZE has a total of seven output options available to it. There are six post divider options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N and DIV2N are independently calculated and are applied to individual output groups ...
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... MHz and 167 MHz (Commercial Temp.) or 150 MHz (Industrial Temp.). Using a Crystal as the Reference Input The input crystal oscillator of the CY27EE16ZE is an important feature because of the flexibility it allows the user in selecting a crystal as a reference frequency source. The input oscillator ...
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... For an external clock source, CapLoad defaults to 1. See Table 5 for CapLoad bit locations and values. The input load capacitors are placed on the CY27EE16ZE die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply and temperature changes ...
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... total The minimum value 129. Register 42H is defined in Table 6. Stable operation of the CY27EE16ZE cannot be guaranteed if REF/Q falls below 250 kHz. Q total are defined in Table 6. PLL Frequency, P Counter The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Q VCO frequency ...
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... Table 9. Charge Pump Settings Charge Pump Setting – Pump(2..0) 000 001 010 011 100 101, 110, 111 Pump(2) Pump(1) CY27EE16ZE DIV1N(2) DIV1N(1) DIV1N(0) DIV2N(2) DIV2N(1) DIV2N(0) . See Table 10, "Register total values below 16 total values above 1023 are needed, use ...
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... CLKSRC1 CLKSRC0 1 for CLOCK4 for CLOCK4 CLKSRC2 CLKSRC1 CLKSRC0 for CLOCK6 for CLOCK6 for CLOCK6 CLKOE for 0 CLKOE for CLOCK5 CLOCK4 CY27EE16ZE be rising edge phase-aligned with CLKSRC0 CLKSRC2 CLKSRC1 for CLOCK2 for CLOCK3 for CLOCK3 1 1 CLKSRC2 for CLOCK5 ...
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... Through random read operations, the master may access any memory location. To perform this type of read operation, first the word address must be set. This is accomplished by sending the address to the CY27EE16ZE as part of a write operation. After the word address is sent, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set ...
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... Repeated Start bit Figure 4. Data Frame Architecture Transition Data Valid to next Bit CLK HIGH CLK LOW CY27EE16ZE STOP Condition 1 Bit 1 Bit 1 Bit Slave Slave Slave ACK ACK ACK 8-bit Register Data (X0H) Stop Signal 1 Bit 1 Bit ...
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... For more information about this package, see, “Application Notes for Surface Mount Assembly of Amkor’s Thermally/Electrically Packages.” Amkor Technology, December 2001. Min. 0 –40 CY27EE16ZE SDAT SCLK + ACK ...
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... Except XTAL pins Current drawn while part is in standby. Description – DDL =2. DDL may be powered at any value between 3.465 and 2.375. DDL CY27EE16ZE Max. Unit 7.0 V 125 °C 100 ° 2000 0.5 ...
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... Ramp time from 1.5V to 2.5V Wait time after a write to EEPROM is initiated by the stop bit until V fails below 2.5V DD CLK , 20–80 LOW DD CLK , 80–20 HIGH DD Square noise spike on input OUTPUTS GND reaches 1.5V, it must ramp to 2.5V within 15 ms. DD CY27EE16ZE Min. Typ. Max. Unit 0.8 1.4 V/ns 0.8 1.4 V/ns ...
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... CY27EE16FZXECT Field Programmed Note: 7. The CY27EE16ZEC-XXX, CY27EE16ZEC-XXXT, CY27EE16ZEI-XXX and CY27EE16ZEI-XXXT are factory-programmed configurations. Factory program- ming is available for high-volume design opportunities of 100Ku/year or more in production. For more details, contact your local Cypress field application engineer or Cypress sales representative. Document #: 38-07440 Rev. *C Figure 8. Duty Cycle Definition t2/ ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges system, provided that the system conforms to the I CY27EE16ZE 51-85168-** 2 C Standard Specification ...
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... Document History Page Document Title: CY27EE16ZE 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM Document Number: 38-07440 Orig. of REV. ECN NO. Issue Date Change ** 116411 10/01/02 CKN *A 121903 12/14/02 RBI *B 127953 07/01/03 IJATMP *C 305737 See ECN RGL Document #: 38-07440 Rev. *C Description of Change New Data Sheet ...