cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 11

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
Sequential Read
Sequential read operations follow the same process as
random reads except that the master issues an acknowledge
instead of a STOP condition after transmission of the first 8-bit
data word. This action results in an incrementing of the internal
address pointer, and subsequently output of the next 8-bit data
word. By continuing to issue acknowledges instead of STOP
conditions, the master may serially read the entire contents of
the 16-kbit EEPROM scratchpad memory. When the internal
SDAT
SCL
SDAT Write
Multiple
Contiguous
Registers
SDAT Read
Current
Address
Read
SDAT Read
Multiple
Contiguous
Registers
Start Signal
Start Signal
Start Signal
START
Condition
7-bit
Device
Address
7-bit
Device
Address
7-bit
Device
Address
R/W = 0
R/W = 1
R/W = 0
SDAT
SCLK
1 Bit
1 Bit
1 Bit
ACK
ACK
ACK
1 Bit
Slave
1 Bit
Slave
1 Bit
Slave
Register
Address
(XXH)
Register
Data
Register
Address
(XXH)
8-bit
8-bit
8-bit
Figure 3. Data Transfer Sequence on the Serial Bus
Figure 5. Data Valid and Data Transition Periods
Address or
Acknowledge
Valid
VIH
VIL
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
Register
Data
(XXH)
Device
Address
+R/W=1
8-bit
7-bit
Repeated
Start bit
Figure 4. Data Frame Architecture
1 Bit
Slave
ACK
CLK
1 Bit
Master
ACK
1 Bit
Master
ACK
Data Valid
(XXH+1)
(XXH)
Register
Data
Data may
be changed
Stop Signal
Register
Data
8-bit
8-bit
HIGH
1 Bit
Slave
ACK
1 Bit
Master
ACK
Register
Data
(XXH+2)
Register
Data
(XXH+1)
8-bit
8-bit
Transition
t
to next Bit
DH
CLK
address pointer points to the FFH word of a EEPROM block,
after the next increment, the pointer will point to the 00H word
of the next block. After incrementing to the FFH word of the
eighth block, the next increment will point the pointer to the
00H word of the 1st EEPROM block. Similarly, sequential
reads within either the EEPROM or SRAM clock configuration
blocks will wrap within the block to the first word of the same
block after reaching the end of either block.
LOW
t
SU
1 Bit
Slave
ACK
1 Bit
Master
ACK
(XXH)
(8FFH)
Register
Data
Register
Data
8-bit
8-bit
16 byte wrap
1 Bit
Slave
ACK
1 Bit
Master
ACK
Register
Data
(X0H)
Register
Data
(000H)
8-bit
8-bit
STOP
Condition
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
Slave
ACK
1 Bit
Master
ACK
CY27EE16ZE
Stop Signal
Stop Signal
Page 11 of 17
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