cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 2

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
Pin Description
Functional Description
The CY27EE16ZE integrates a 16-kbit EEPROM scratchpad
and a clock generator that features Cypress’s programmable
clock core. An industry standard I
interface (SPI) is used to program the scratchpad and clock
core.
16-kbit EEPROM
The 16-kbit EEPROM scratchpad is organized in eight blocks
x 256 words x 8 bits. Each of the eight 2-kbit EEPROM
scratchpad blocks, a 2-kbit clock configuration EEPROM
block, and a 2-kbit volatile clock configuration SRAM block,
have their own 7-bit device address. The device address is
combined with a Read/Write bit as the LSB and is sent after
each start bit.
Clock Features
The programmable clock core is configured with the following
features:
Outputs: Six outputs and two programmable linear dividers.
The output swing of CLOCK1 through CLOCK4 is set by VDDL
(2.5V or 3.3V). The output swing of CLOCK5 and CLOCK6 is
set by VDD (3.3V).
Note:
XIN
VDD
CLOCK6
AVDD
SDAT
AVSS
VSSL
CLOCK1
CLOCK2
OE/PDM
VDDL
CLOCK3
SCL
CLOCK4
VSS
VCXO/WP
CLOCK5
XOUT
1. Float XOUT if XIN is externally driven.
• Crystal Oscillator: Programmable drive and load, support
• VCXO: Analog or digital control
• Inputs and I/Os: Programmable input muxes drive write
• PLL: Programmable P, Q, offset, and loop filter parameters.
Name
for external references up to 166 MHz. See "Reference
Frequency (REF)", page 5
protect (WP), analog VCXO control, output enable (OE),
and power down mode (PDM) functions
[1]
1
2, 19
3
4
5
6
7
8
9
10
11,14
12
13
15
16
17
18
20
Pin Number
Reference crystal input
3.3V voltage supply
Clock output 6
3.3V analog voltage supply
Data input for serial programming
Analog ground
Output ground
Clock output 1
Clock output 2
Output enable or power-down mode enable
Output voltage supply
Clock output 3
Clock signal input for serial programming
Clock output 4
Ground
Analog control input for VCXO or write protect (user-configurable)
Clock output 5
Reference crystal output
Description
2
C serial programming
Clock configuration is stored in a dedicated 2-kbit block of
nonvolatile EEPROM and a 2-kbit block of volatile SRAM. The
SPI is used to write new configuration data to the on-chip
programmable registers that are defined within the clock
configuration memory blocks. Other, custom configurations,
that include custom VCXO, Spread Spectrum for EMI
reduction, Fractional N and frequency select pins (FS) are
programmable; contact factory for details.
Write Protect (WP) – Active HIGH
The default clock configuration of the CY27EE16ZE has pin
17 configured as WP. When a logical HIGH level input is
asserted on this pin, the write protect feature (WP) will inhibit
writing to the EEPROM. This protects EEPROM bits from
being changed, while allowing full read access to EEPROM.
Writing to SRAM is allowed with WP enabled. When this pin is
held at a logical LOW level, WP is disabled and data can be
written to EEPROM.
Analog Adjust for Voltage Controlled Crystal Oscillator
(VCXO)
Pin 17 can be programmed, with the SPI, to function as the
analog control for the VCXO. Then, pin 17 provides ±150 ppm
adjustment of the crystal oscillator frequency (in order to use
the VCXO, the crystal must have a minimum of ±150 ppm pull
range and meet the pullable crystal specifications as shown in
Table 14 on page 12). The crystal oscillator frequency is pulled
lower by at least 150 ppm when 0V is applied to VCXO, pulled
higher by at least 150 ppm when V
oscillator frequency will have a linear dependence on the
voltage level applied to pin 17, VCXO, within a range from 0V
to V
information.
DD
. See section "Device Addressing", page 10 for more
DD
is applied to VCXO. The
CY27EE16ZE
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