cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 14

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
AC Electrical Specifications (V
Test and Measurement Set-up
DC
ER
EF
t
t
t
t
t
Memory Section Specifications
F
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
5
9
10
VDDramp
VDDpowerdown
L
H
SP
AA
BUFF
HDSTART
SUSTART
DH
SU
RI
FI
SUSTOP
DH
WR
5. Not 100% tested.
6. The power supply voltage must increase monotonically from 0 to 2.5V; once V
Parameter
SCL
O
O
[5]
Clock Output Duty Cycle
Rising Edge Rate
Falling Edge Rate
Output to Output Skew
Clock Jitter
PLL Lock Time
Power Supply Ramp
Power Supply Power Down
after Write
SCL input frequency
Clock Pulse Low
Clock Pulse High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free
before a new transmission
may start
Start Hold Time
Start Set-up Time
Data in Hold Time
Data in Set-up time
Inputs rise time
Inputs fall time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
V
DD
Name
0.1 µF
DD
= 3.3V)
Square noise spike on input
f
f
See Figure 8
Output Clock Edge Rate, Measured from 20%
to 80% of V
Output Clock Edge Rate, Measured from 80%
to 20% of V
For related clock outputs
Maximum absolute jitter (EEPROM quiet)
(during EEPROM reads)
(during EEPROM writes)
Ramp time from 1.5V to 2.5V
Wait time after a write to EEPROM is initiated
by the stop bit until V
CLK
CLK
OUT
OUT
LOW
HIGH
< 150 MHz
> 150 MHz, or f
OUTPUTS
, 20–80% of V
, 80–20% of V
GND
DD,
DD,
C
C
Description
LOAD
LOAD
DD
OUT
DD
reaches 1.5V, it must ramp to 2.5V within 15 ms.
= 15 pF See Figure 9.
= 15 pF See Figure 9.
DD
DD
fails below 2.5V
= f
REF
[6]
C
LOAD
CLK out
Min.
100
0.8
0.8
0.6
0.1
1.2
0.6
0.6
0.6
45
40
20
50
0
Typ.
250
300
350
CY27EE16ZE
1.4
1.4
50
50
Max.
250
400
300
300
Page 14 of 17
1.2
0.9
55
60
60
15
50
20
Unit
V/ns
V/ns
kHz
ms
ms
ms
ms
ms
ps
ps
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
µs
ns
%
[+] Feedback