74f114sc NXP Semiconductors, 74f114sc Datasheet
74f114sc
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74f114sc Summary of contents
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Philips Semiconductors Dual J-K negative edge-triggered flip-flop with common clock and reset DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and ...
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Philips Semiconductors Dual J-K negative edge-triggered flip-flop with common clock and reset LOGIC DIAGRAM FUNCTION TABLE INPUTS ...
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Philips Semiconductors Dual J-K negative edge-triggered flip-flop with common clock and reset RECOMMENDED OPERATING CONDITIONS SYMBOL SYMBOL PARAMETER PARAMETER V Supply voltage CC V High-level input voltage IH V Low-level input voltage IL I Input clamp current IK I High-level ...
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Philips Semiconductors Dual J-K negative edge-triggered flip-flop with common clock and reset AC ELECTRICAL CHARACTERISTICS SYMBOL SYMBOL PARAMETER PARAMETER f Maximum clock frequency MAX t Propagation delay PLH PHL t Propagation delay PLH t ...
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Philips Semiconductors Dual J-K negative edge-triggered flip-flop with common clock and reset Jn, Kn SDn Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock Jn, Kn ...
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Philips Semiconductors Dual J-K negative edge-triggered flip-flop with common clock and reset TEST CIRCUIT AND WAVEFORMS OUT PULSE D.U.T. GENERATOR R T Test Circuit for Totem-Pole Outputs DEFINITIONS Load resistor; L see AC ...