74f114sc NXP Semiconductors, 74f114sc Datasheet - Page 4

• Manufacturer Part Number: 74f114sc
• Description: Dual J-k Negative Edge-triggered Flip-flop With Common Clock And Reset
• Manufacturer: NXP Semiconductors

Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
AC SETUP REQUIREMENTS
AC WAVEFORMS
For all waveforms, V
The shaded areas indicate when the input is permitted to change for predictable output performance.
1996 Mar 14
SYMBOL
SYMBOL
SYMBOL
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
MAX
PLH
PHL
PLH
PHL
S
S
h
h
W
W
W
REC
Dual J-K negative edge-triggered flip-flop
with common clock and reset
(H)
(L)
(H)
(L)
(H)
(L)
(L)
Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width
Propagation delay
CP to Qn or Qn
Propagation delay
SDn, RD to Qn or Qn
Maximum clock frequency
Setup time, High or Low
Jn, Kn to CP
Hold time, High or Low
Jn, Kn to CP
CP Pulse width
High or Low
SDn, RD Pulse width
Low
Recovery time
SDn, RD to CP
M
= 1.5V.
PARAMETER
PARAMETER
PARAMETER
PARAMETER
Jn, Kn
CP
Qn
Qn
V
t
s
V
M
(L)
M
Kn
Jn
t
h
V
(L)
t
t
Waveform 2,3
Waveform 2,3
Waveform 2,3
PHL
PLH
M
CONDITION
CONDITION
Waveform 1
Waveform 1
Waveform 1
Waveform 1
Waveform 1
t
w
TEST
TEST
TEST
TEST
(L)
V
V
V
M
f
M
M
max
4
t
w
C
C
MIN
MIN
2.0
2.0
2.0
2.0
4.0
3.5
0.0
0.0
4.5
4.5
4.5
4.5
(H)
85
L
L
= 50pF, R
= 50pF, R
V
t
T
T
s
V
V
M
(H)
amb
amb
CC
CC
Jn
Kn
TYP
TYP
100
= +5.0V
5.0
5.5
4.5
4.5
= +5.0V
= +25 C
= +25 C
t
h
V
V
(H)
t
L
L
M
t
PLH
M
PHL
V
= 500
= 500
V
M
M
MAX
MAX
6.5
7.5
6.5
6.5
LIMITS
LIMITS
C
C
T
T
V
V
L
L
amb
amb
MIN
MIN
CC
2.0
2.0
2.0
2.0
CC
5.0
4.0
0.0
0.0
5.0
5.0
5.0
5.0
80
= 50pF, R
= 50pF, R
= +5.0V
= +5.0V
= 0 C to +70 C
= 0 C to +70 C
L
L
= 500
= 500
MAX
MAX
10%
7.5
8.5
7.5
7.5
10%
Product specification
74F114
UNIT
UNIT
UNIT
UNIT
MHz
SF00114
ns
ns
ns
ns
ns
ns
ns