isl88731c Intersil Corporation, isl88731c Datasheet - Page 12

• Manufacturer Part Number: isl88731c
• Description: Smbus Level 2 Battery Charger
• Manufacturer: Intersil Corporation

Undervoltage Detect and Battery Trickle
Charging
If the voltage at CSON falls below 2.5V ISL88731C
reduces the charge current limit to 128mA to trickle
charge the battery. When the voltage rises above 2.7V,
the charge current reverts to the programmed value in
the ChargeCurrent register.
Over-Temperature Protection
If the die temp exceeds +150°C, it stops charging. Once
the die temp drops below +125°C, charging will start up
again.
Overvoltage Protection
ISL88731C has an Overvoltage Protection circuit that
limits the output voltage when the battery is removed or
disconnected by a pulse charging circuit. If CSON
exceeds the output voltage set point in the charge
voltage register by more than 300mV, an internal
comparator pulls VCOMP down and turns off both upper
and lower FETs of the buck as in Figure 17. There is a
delay of approximately 1µs between V
OVP trip point and pulling VCOMP, LGATE and UGATE low.
After UGATE and LGATE are turned OFF, inductor current
continues to flow through the body diode of the lower
FET and V
reaches zero.
FIGURE 17. OVERVOLTAGE PROTECTION IN ISL88731C
The System Management Bus
The System Management Bus (SMBus) is a 2-wire bus
that supports bidirectional communications. The protocol
is described briefly here. More detail is available from
www.smbus.org.
INDUCTOR CURRENT
PHASE
OUT
BATTERY CURRENT
continues to rise until inductor current
12
V
OUT
OUT
exceeding the
ISL88731C
General SMBus Architecture
Data Validity
The data on the SDA line must be stable during the HIGH
period of the SCL, unless generating a START or STOP
condition. The HIGH or LOW state of the data line can
only change when the clock signal on the SCL line is
LOW. Refer to Figure 18.
START and STOP Conditions
As shown in Figure 19, START condition is a
HIGH-to-LOW transition of the SDA line while SCL is
HIGH.
The STOP condition is a LOW-to-HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be
sent before each START condition.
SDA
SDA
SCL
SCL
CONDITION
CPU
START
FIGURE 19. START AND STOP WAVEFORMS
S
SMBUS MASTER
CONTROL
CONTROL
DATA VALID
SDA
SCL
DATA LINE
FIGURE 18. DATA VALIDITY
STABLE
OUTPUT
INPUT
INPUT
OUTPUT
VDDSMB
ALLOWED
OF DATA
CHANGE
SLAVE DEVICES
TO OTHER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
CONTROL
CONTROL
CONTROL
CONTROL
SMBUS SLAVE
SMBUS SLAVE
CONDITION
SCL
SDA
SCL
SDA
September 9, 2010
STOP
P
REGISTERS,
REGISTERS,
MACHINE,
MACHINE,
MEMORY,
MEMORY ,
FN6978.1
STATE
STATE
ETC
ETC