isl6334ar5368 Intersil Corporation, isl6334ar5368 Datasheet
isl6334ar5368
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isl6334ar5368 Summary of contents
Page 1
... The ISL6334AR5368 is designed to be completely compliant with Intel VR11.1 specifications. It accurately reports the load current via IMON pin to the microprocessor, which sends an active low PSI# signal to the controller at low power mode ...
Page 2
... Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# OFS IMON 2 ISL6334AR5368 PART TEMP. RANGE MARKING (°C) - +70 ISL6334AR5368 (40 LD QFN) TOP VIEW GND ...
Page 3
... Quad ISL6610, ISL6610A 5V Quad NOTE: Note: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow dual footprint layout to optimize MOSFET selection and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous Channels. 3 ISL6334AR5368 COMMENTS GATE DIODE DRIVE EMULATION DROP (DE) ...
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... ISL6334AR5368 Block Diagram VDIFF - RGND X1 + VSEN SOFT-START + OVP - FAULT LOGIC +175mV SS VID7 VID6 VID5 DYNAMIC VID4 VID VID3 D/A VID2 VID1 VID0 DAC OFS OFFSET REF FB COMP 1.11V + OCP - IMON 1.11V VR_HOT THERMAL MONITOR VR_FAN TM 4 ISL6334AR5368 VR_RDY FS PSI# CLOCK AND RAMP GENERATOR ...
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... PWM3 ISEN3- VR_HOT VIN ISEN3+ EN_PWR +5V GND PWM4 IMON ISEN4- ISEN4+ TCOMP TM OFS FS +5V +5V NTC NTC: NTHS0805N02N6801, 6.8kΩ, VISHAY 5 ISL6334AR5368 +12V PVCC VCC ISL6622 DRIVER PWM +12V PVCC VCC ISL6612 DRIVER PWM +12V PVCC VCC ISL6612 DRIVER PWM +12V SS PVCC VCC ...
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... VR_FAN ISEN3- VR_HOT ISEN3+ VIN EN_PWR +5V GND PWM4 ISEN4- IMON ISEN4+ TCOMP TM OFS FS +5V +5V NTC NTC: NTHS0805N02N6801, 6.8kΩ, VISHAY 6 ISL6334AR5368 +12V PVCC VCC ISL6612 DRIVER PWM DAC REF +12V PVCC VCC ISL6612 DRIVER PWM +12V PVCC VCC ISL6612 DRIVER PWM +12V ...
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... ISEN2+ VR_FAN ISEN2- VR_HOT PWM2 VIN EN_PWR PWM4 +5V GND ISEN4- ISEN4+ IMON TCOMP TM OFS FS +5V NTC 5V NTC: NTHS0805N02N6801, 6.8kΩ, VISHAY 7 ISL6334AR5368 +12V VCC DAC GND REF ISL6614 DRIVER PWM1 PWM2 +12V VCC GND ISL6614 DRIVER SS PWM1 5V PWM2 VIN BOOT1 UGATE1 PHASE1 ...
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... VID Pull-up VID Input Low Level VID Input High Level Max DAC Source Current Max DAC Sink Current Max REF Source/Sink Current 8 ISL6334AR5368 Thermal Information Thermal Resistance (Notes 0. 6x6 QFN Package . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile ...
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... Overcurrent Trip Level for Average Current At Normal CCM PWM Mode Overcurrent Trip Level for Average Current at PSI# Mode Peak Current Limit for Individual Channel IMON Clamped and OCP Trip Level 9 ISL6334AR5368 TEST CONDITIONS Offset resistor connected to ground Voltage below VCC, offset resistor connected to VCC R = 100kΩ ...
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... During soft-start, VDAC rises from 0V to 1.1V first and then ramp to VID voltage after receiving valid VID. 6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle. 10 ISL6334AR5368 TEST CONDITIONS With external pull-up resistor connected to VCC With 1.24k resistor pull-up to VCC, I ...
Page 11
... Connect this pin through an NTC thermistor to GND and a resistor to VCC of the controller. The voltage at this pin is reverse proportional to the VR temperature. The ISL6334AR5368 monitors the VR temperature based on the voltage at the TM pin and outputs VR_HOT and VR_FAN signals. VR_HOT - VR_HOT is used as an indication of high VR temperature ...
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... The ISL6334AR5368 controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagrams on pages page 5, 7, and 6 provide top level views of multiphase power conversion using the ISL6334AR5368 controller ...
Page 13
... PWM and PSI# Operation The timing of each channel is set by the number of active channels. The default channel setting for the ISL6334AR5368 is four. The switching cycle is defined as the time between PWM pulse termination signals of each channel. The cycle time of the pulse signal is the inverse of the switching frequency set by the resistor between the FS pin and ground ...
Page 14
... SWITCHING FREQUENCY (Hz) FIGURE 3. SWITCHING FREQUENCY ISL6334AR5368 Current Sensing The ISL6334AR5368 senses current continuously for fast response. The ISL6334AR5368 supports inductor DCR sensing, or resistive sensing techniques. The associated channel current sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, I The sense current, I current ...
Page 15
... DAC) and offset errors in the OFS current source, remote-sense and error amplifiers. Intersil specifies the guaranteed tolerance of (EQ. 7) the ISL6334AR5368 to include the combined tolerances of each of these elements. The sensed average current I This current will develop voltage drop across the resistor between FB and VDIFF pins for droop control ...
Page 16
... OUT FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT The ISL6334AR5368 incorporates an internal differential remote-sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point, resulting in a more accurate means of sensing output voltage ...
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... ISL6334AR5368 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 1 0 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 ...
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... ISL6334AR5368 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 1 0 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 ...
Page 19
... ISEN Output-Voltage Offset Programming The ISL6334AR5368 allows the designer to accurately adjust the offset voltage. When a resistor, R connected between OFS to VCC, the voltage across it is regulated to 1.6V. This causes a proportional current (I to flow into OFS connected to ground, the voltage OFS across it is regulated to 0 ...
Page 20
... Vboot voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period t ISL6334AR5368 reads the VID signals. If the VID code is valid, ISL6334AR5368 will initiate the second soft-start ramp until the voltage reaches the VID voltage minus offset voltage. ...
Page 21
... Once the controller detects valid VID input, the OVP trip point will be changed to DAC plus 175mV. Two actions are taken by ISL6334AR5368 to protect the microprocessor load when an overvoltage condition occurs. At the inception of an overvoltage event, all PWM outputs (EQ. 17) are commanded low instantly (less than 20ns) ...
Page 22
... If one channel current exceeds the reference current, ISL6334AR5368 will pull PWM signal of this channel to low for the rest of the switching cycle. This PWM signal can be turned on next cycle if the sensed channel current is less than the 129µ ...
Page 23
... Integrated Temperature Compensation When the TCOMP voltage is equal or greater than VCC/15, 100 120 140 ISL6334AR5368 will utilize the voltage at TM and TCOMP pins to compensate the temperature impact on the sensed current. The block diagram of this function is shown in Figure 15 ...
Page 24
... VDIFF pins reverse proportional to the temperature. The external temperature compensation network can only (EQ. 21) compensate the temperature impact on the droop, while it has no impact to the sensed current inside ISL6334AR5368. Therefore, this network cannot compensate for the temperature impact on the overcurrent protection function. (EQ. 22) ...
Page 25
... Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; 25 ISL6334AR5368 the lower-MOSFET body-diode reverse-recovery charge, Q and the upper MOSFET r When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground ...
Page 26
... I is the full load current of the specific application, FL and VR is the desired voltage droop under the full DROOP load condition. 26 ISL6334AR5368 can be chosen Based on the desired loadline R OCP resistor can be calculated using Equation 33 where N is the active channel number, R ...
Page 27
... DROOP - VDIFF FIGURE 17. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6334AR5368 CIRCUIT The feedback resistor has already been chosen as FB outlined in “Load-Line Regulation Resistor” on page 26. Select a target bandwidth for the compensated system, f The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency ...
Page 28
... MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. 28 ISL6334AR5368 (EQ. 37) FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT (EQ. 38) FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT (EQ. 39) ⎞ ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 ISL6334AR5368 Layout Considerations O The following layout strategies are intended to minimize the ...
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... Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 30 ISL6334AR5368 4X 4.5 36X 0. 40X ± BOTTOM VIEW ± SIDE VIEW ( 36X ...