isl6262a Intersil Corporation, isl6262a Datasheet - Page 20

• Manufacturer Part Number: isl6262a
• Description: Two-phase Core Controller Santa Rosa, Imvp-6+
• Manufacturer: Intersil Corporation

The first current, labeled I
Specifications on page 3 as 42µA. This current is used
during soft-start. The second current, I
the larger of the two currents, labeled I
Table Electrical Specifications on page 3 . This total current
is typically 205µA with a minimum of 180µA.
The IMVP-6+ specification reveals the critical timing
associated with regulating the output voltage. The symbol,
SLEWRATE, as given in the IMVP-6+ specification will
determine the choice of the SOFT capacitor, C
Equation 1.
Using a SLEWRATE of 10mV/µs and the typical I
given in the Electrical Specification table of 205µA, C
as shown in Equation 2.
A choice of 0.015µF would guarantee a SLEWRATE of
10mV/µs is met for the minimum I
Electrical Specification table. This choice of C
control the Start-Up slewrate as well. One should expect the
output voltage to slew to the Boot value of 1.2V at a rate
given by Equation 3.
Selecting RBIAS
To properly bias the ISL6262A, a reference current is
established by placing a 147kΩ, 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate
10µA current source from which the OCSET reference
current can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the RBIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-Up Operation - CLK_EN# and PGOOD
The ISL6262A provides a 3.3V logic output pin for
CLK_EN#. The 3V3 pin allows for a system 3.3V source to
be connected to separated circuitry inside the ISL6262A,
solely devoted to the CLK_EN# function. The output is a
3.3V CMOS signal with 4mA sourcing and sinking capability.
This implementation removes the need for an external
pull-up resistor on this pin, and due to the normal level of this
signal being a low, removes the leakage path from the 3.3V
supply to ground through the pull-up resistor. This reduces
the 3.3V supply current that would occur under normal
operation with a pull-up resistor and prolongs battery life. For
C
C
dV
-------
dt
SOFT
SOFT
=
-------------------
C
SOFT
=
=
I
SS
----------------------------------- -
SLEWRATE
205μA
=
I
GV
---------------------- -
0.015μF
⁄
41μA
(
10mV 1μs
⁄
=
SS
2.8mV μs
, is given in the Table Electrical
20
)
⁄
GV
value given in the
2
GV
sums with I
in the
SOFT
SOFT
GV
SS
will then
, by
SOFT
value
(EQ. 1)
(EQ. 2)
(EQ. 3)
to get
ISL6262A
is
noise immunity, the 3.3V supply should be decoupled to
digital ground rather than to analog ground.
As mentioned in “Theory of Operation” on page 16,
CLK_EN# is logic level high at start-up until approximately
43µs after the V
Approximately 43µs after V
CLK_EN# goes low, triggering an internal timer for the
IMVP6_PWRGD signal. This timer allows IMVP-6_PWRGD
to go high approximately 6.8ms after CLK_EN# goes low.
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6262A are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are Vcc_sense and
Vss_sense respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
These traces should be laid out as noise sensitive traces. For
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode filters to analog ground on VSEN and RTN as shown in
Figure 37.
Intersil recommends the use of the R
connected to V
These resistors provide voltage feedback in the event that
the system is powered up without a processor installed.
These resistors typically range from 20 to 100Ω.
OUT
CC
-core is in regulation at the Boot level.
and ground as shown in Figure 37.
CC
-core are within regulation,
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and R
December 23, 2008
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FN6343.1