SST89V54RD2 Silicon Storage Technology, Inc., SST89V54RD2 Datasheet - Page 39

• Manufacturer Part Number: SST89V54RD2
• Description: Flashflex51 Mcu
• Manufacturer: Silicon Storage Technology, Inc.

FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
6.0 SERIAL I/O
6.1 Full-Duplex, Enhanced UART
The device serial I/O port is a full-duplex port that allows
data to be transmitted and received simultaneously in
hardware by the transmit and receive registers, respec-
tively, while the software is performing other tasks. The
transmit and receive registers are both located in the
Serial Data Buffer (SBUF) special function register. Writ-
ing to the SBUF register loads the transmit register, and
reading from the SBUF register obtains the contents of
the receive register.
The UART has four modes of operation which are selected
by the Serial Port Mode Specifier (SM0 and SM1) bits of
the Serial Port Control (SCON) special function register. In
all four modes, transmission is initiated by any instruction
that uses the SBUF register as a destination register.
Reception is initiated in mode 0 when the Receive Interrupt
(RI) flag bit of the Serial Port Control (SCON) SFR is
cleared and the Reception Enable/ Disable (REN) bit of the
©2007 Silicon Storage Technology, Inc.
FIGURE
6-1: Framing Error Block Diagram
SMOD1
SM0/FE
SMOD0
SM1
SM2
BOF
REN
POF
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD0 = 0)
To UART framing error control
GF1
TB8
39
RB8
GF0
SCON register is set. Reception is initiated in the other
modes by the incoming start bit if the REN bit of the SCON
register is set.
6.1.1 Framing Error Detection
Framing Error Detection is a feature, which allows the
receiving controller to check for valid stop bits in modes 1,
2, or 3. Missing stops bits can be caused by noise in serial
lines or from simultaneous transmission by two CPUs.
Framing Error Detection is selected by going to the PCON
register and changing SMOD0 = 1 (see Figure 6-1). If a
stop bit is missing, the Framing Error bit (FE) will be set.
Software may examine the FE bit after each reception to
check for data errors. After the FE bit has been set, it can
only be cleared by software. Valid stop bits do not clear FE.
When FE is enabled, RI rises on the stop bit, instead of the
last data bit (see Figure 6-2 and Figure 6-3).
PD
TI
IDL
RI
SCON
PCON
(98H)
(87H)
1255 F16.0
S71255-10-000
Data Sheet
12/07