SST89V54RD2 Silicon Storage Technology, Inc., SST89V54RD2 Datasheet - Page 65

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SST89V54RD2

Manufacturer Part Number
SST89V54RD2
Description
Flashflex51 Mcu
Manufacturer
Silicon Storage Technology, Inc.
Datasheet

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FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
©2007 Silicon Storage Technology, Inc.
1. Under steady state (non-transient) conditions, I
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V
3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF.
4. Capacitive loading on Ports 0 and 2 may cause the V
5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
Maximum I
Maximum I
Maximum I
If I
listed test conditions.
due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
when the address bits are stabilizing.
its maximum value when V
OL
exceeds the test condition, V
OL
OL
OL
per port pin:
per 8-bit port:
total for all outputs: 71mA
IN
is approximately 2V.
15mA
26mA
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the
OL
must be externally limited as follows:
OH
on ALE and PSEN# to momentarily fall below the V
65
OL
s of ALE and Ports 1 and 3. The noise
DD
- 0.7 specification
S71255-10-000
Data Sheet
12/07

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