ad5331bru-reel7 Analog Devices, Inc., ad5331bru-reel7 Datasheet - Page 17

• Manufacturer Part Number: ad5331bru-reel7
• Description: 2.5 V To 5.5 V, 115 Ua, Parallel Interface Single Voltage-output 8-/10-/12-bit Dacs
• Manufacturer: Analog Devices, Inc.

Bipolar Operation Using the AD5330/AD5331/AD5340/AD5341
The AD5330/AD5331/AD5340/AD5341 have been designed
for single supply operation, but bipolar operation is achievable
using the circuit shown in Figure 36. The circuit shown has been
configured to achieve an output voltage range of –5 V < V
+5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
V
where:
D is the decimal equivalent of the code loaded to the DAC, N is
DAC resolution and V
With:
Decoding Multiple AD5330/AD5331/AD5340/AD5341
The CS pin on these devices can be used in applications to decode
a number of DACs. In this application, all DACs in the system
receive the same data and WR pulses, but only the CS to one of
the DACs will be active at any one time, so data will only be
written to the DAC whose CS is low. If multiple AD5341s are
being used, a common HBEN line will also be required to
determine if the data is written to the high-byte or low-byte
register of the selected DAC.
AD589 WITH V
O
V
R1 = R3 = 10 kΩ
R2 = R4 = 20 kΩ and V
V
= [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V
REF
OUT
EXT
REF
AD780/REF192
WITH V
= 2.5 V
GND
= (10 × D/2
V
OR
IN
DD
V
DD
= 5V
OUT
= 2.5V
N
0.1 F
0.1 F
) – 5
REF
is the reference voltage input.
DD
V
AD5330/AD5331/
AD5340/AD5341
REF
10 F
= 5 V.
V
DD
GND
V
DD
= 5V
V
10k
OUT
REF
R3
× D/
10k
R1
2
N
)] – R4 × V
R2
20k
20k
R4
+5V
–5V
REF
O
/R3
<
5V
The 74HC139 is used as a 2- to 4-line decoder to address any
of the DACs in the system. To prevent timing errors, the enable
input should be brought to its inactive state while the coded
address inputs are changing state. Figure 37 shows a diagram of a
typical setup for decoding multiple devices in a system. Once
data has been written sequentially to all DACs in a system, all the
DACs can be updated simultaneously using a common LDAC
line. A common CLR line can also be used to reset all DAC
outputs to zero.
ADDRESS
ENABLE
CODED
HBEN
LDAC
CLR
WR
AD5330/AD5331/AD5340/AD5341
1G
1A
1B
74HC139
DGND
V
V
CC
DD
1Y0
1Y1
1Y2
1Y3
*AD5341 ONLY
HBEN*
WR
LDAC
CLR
CS
HBEN*
WR
LDAC
CLR
CS
HBEN*
WR
LDAC
CLR
CS
HBEN*
WR
LDAC
CLR
CS
AD5330/AD5331/
AD5330/AD5331/
AD5330/AD5331/
AD5330/AD5331/
AD5340/AD5341
AD5340/AD5341
AD5340/AD5341
AD5340/AD5341
INPUTS
INPUTS
INPUTS
INPUTS
DATA
DATA
DATA
DATA