ad5331bru-reel7 Analog Devices, Inc., ad5331bru-reel7 Datasheet - Page 5

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ad5331bru-reel7

Manufacturer Part Number
ad5331bru-reel7
Description
2.5 V To 5.5 V, 115 Ua, Parallel Interface Single Voltage-output 8-/10-/12-bit Dacs
Manufacturer
Analog Devices, Inc.
Datasheet
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13–20
LDAC
GAIN
BUF
CLR
DB
DB
WR
CS
. .
7
0
Mnemonic
BUF
NC
V
V
GND
CS
WR
GAIN
CLR
LDAC
PD
V
DB
REF
OUT
DD
INTER-
LOGIC
FACE
0
–DB
AD5330 FUNCTIONAL BLOCK DIAGRAM
RESET
7
POWER-ON
REGISTER
RESET
INPUT
Function
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
No Connect.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. This controls whether the output range from the DAC is 0–V
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB
REGISTER
DAC
AD5330 PIN FUNCTION DESCRIPTIONS
8-BIT
DAC
V
REF
BUFFER
7
V
AD5330
is the MSB of these eight bits.
DD
POWER-DOWN
LOGIC
PD
GND
AD5330/AD5331/AD5340/AD5341
V
OUT
AD5330 PIN CONFIGURATION
LDAC
GAIN
V
V
GND
BUF
CLR
OUT
REF
WR
NC
CS
10
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD5330
8-BIT
REF
or 0–2 V
20
19
18
17
16
15
14
13
12
11
DB
DB
DB
DB
DB
DB
DB
DB
V
PD
DD
7
6
5
4
3
2
1
0
REF.

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