ltc4269cdkd-2 Linear Technology Corporation, ltc4269cdkd-2 Datasheet - Page 16

• Manufacturer Part Number: ltc4269cdkd-2
• Description: Ieee 802.3at High Power Pd And Synchronous Forward Controller With Aux Support
• Manufacturer: Linear Technology Corporation

LTC4269-2
APPLICATIONS INFORMATION
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4269-2 presents a Class 4 load cur-
rent. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
The PSE repeats this sequence, signaling the 2nd Clas-
sifi cation and 2nd mark event occurrence. This alerts the
LTC4269-2 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4269-2 charges
up the reservoir capacitor C1 with a controlled inrush
current. When C1 is fully charged, and the LTC4269-2
declares power good, the T2P pin presents an active low
signal, or low impedance output with respect to V
The T2P output becomes inactive when the LTC4269-2
input voltage falls below the PoE undervoltage lockout
threshold.
SIGNATURE CORRUPT DURING MARK
As a member of the IEEE 802.3at working group, Linear
noted that it is possible for a Type 2 PD to receive a false
indication of a 2-event classifi cation if a PSE port is pre-
charged to a voltage above the detection voltage range
before the fi rst detection cycle. The IEEE working group
modifi ed the standard to prevent this possibility by requir-
ing a Type 2 PD to corrupt the signature resistance during
the mark event, alerting the PSE not to apply power. The
LTC4269-2 conforms to this standard by internally cor-
rupting the signature resistance. This also discharges the
port before the PSE begins the next detection cycle.
PD STABILITY DURING CLASSIFICATION
Classifi cation presents a challenging stability problem due
to the wide range of possible classifi cation load current.
The onset of the classifi cation load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classifi cation with the
onset and removal of the classifi cation load current.
The LTC4269-2 prevents this oscillation by introducing a
voltage hysteresis window between the detection and clas-
sifi cation ranges. The hysteresis window accommodates
16
PORTN
.
the voltage changes a PD encounters at the onset of the
classifi cation load current, thus providing a trouble-free
transition between detection and classifi cation modes.
The LTC4269-2 also maintains a positive I-V slope through-
out the classifi cation range up to the on voltage. In the
event a PSE overshoots beyond the classifi cation voltage
range, the available load current aids in returning the PD
back into the classifi cation voltage range. (The PD input
may otherwise be “trapped” by a reverse-biased diode
bridge and the voltage held by the 0.1μF capacitor.)
INRUSH CURRENT
Once the PSE detects and optionally classifi es the PD, the
PSE then applies power to the PD. When the LTC4269-2 port
voltage rises above the on voltage threshold, LTC4269-2
connects V
MOSFET.
To control the power-on surge currents in the system, the
LTC4269-2 provides a fi xed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
The LTC4269-2 keeps the PD inrush current below the
PSE current limit to provide a well-controlled power-up
characteristic that is independent of the PSE behavior.
This ensures a PD using the LTC4269-2 interoperability
with any PSE.
POE UNDERVOLTAGE LOCKOUT
The IEEE 802.3af/at specifi cation for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specifi cation provides an adequate
voltage to begin PD operation, and to discontinue PD op-
eration when the port voltage is too low. In addition, this
specifi cation allows PD designs to incorporate an on-off
hysteresis window to prevent start-up oscillations.
The LTC4269-2 features a PoE undervoltage lockout
(UVLO) hysteresis window (See Figure 5) that conforms
with the IEEE 802.3af/at specifi cation and accommodates
the voltage drop in the cable and input diode bridge at the
onset of the inrush current.
Once C1 is fully charged, the LTC4269-2 turns on its inter-
nal MOSFET and passes power to the PD. The LTC4269-2
NEG
to V
PORTN
through the internal power
42692f