mg82fel308 Megawin Technology, mg82fel308 Datasheet
mg82fel308
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mg82fel308 Summary of contents
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... Megawin Technology Co., Ltd. MG82FE(L)308/316 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D Data Sheet Ver 0.04 1/84 ...
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... Port 4 Register ............................................................................................................. 30 10.2.6. Port 5 Register ............................................................................................................. 30 10.2.7. Port 6 Register ............................................................................................................. 31 10.2.8. Port 7 Register ............................................................................................................. 31 11. Interrupt...................................................................................................... 32 11.1. Interrupt Structure ............................................................................................................... 32 11.2. Interrupt Register ................................................................................................................ 33 12. Timers/Counters......................................................................................... 39 12.1. Timer0 and Timer1.............................................................................................................. 39 12.1.1. Mode 0 Structure .......................................................................................................... 39 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG82FE(L)308/316 Content Preliminary, v 0.04 2/84 ...
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... In System Programming (ISP) ................................................................... 73 18. In Application Programming (IAP).............................................................. 76 19. Auxiliary SFRs............................................................................................ 77 20. Absolute Maximum Rating ......................................................................... 79 21. Electrical Characteristics............................................................................ 80 21.1. DC Characteristics .............................................................................................................. 80 22. Package Dimension ................................................................................... 82 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG82FE(L)308/316 Preliminary, v 0.04 3/84 ...
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... MEGAWIN MAKE YOU WIN 23. Revision History ......................................................................................... 84 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG82FE(L)308/316 Preliminary, v 0.04 4/84 ...
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... Power-down mode the device can be waked up by the external interrupts. And, the user can further reduce the power consumption by using the 8-bit system clock pre-scaler to slow down the operating speed. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG82FE(L)308/316 Preliminary ...
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... MG82FL308/316: 2.4V~3.6V, minimum 2.7V requirement in flash write operation(ISP/IAP/……) ━ Operation frequency : 25MHz(max) External crystal mode ━ Internal RC-oscillator (12MHz) with +/- 4% frequency drift @ -40 ~ 85℃, output on XTAL2/P6.0 ━ This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG82FE(L)308/316 Preliminary, v 0.04 6/84 ...
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... MAKE YOU WIN Operating Temperature: Industrial (-40℃ to +85℃)* ━ Package Types: TQFP64: MG82FE(L)316AD64 ━ LQFP48: MG82FE(L)308AD48 ━ *: Tested by sampling. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG82FE(L)308/316 Preliminary, v 0.04 7/84 ...
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... MEGAWIN MAKE YOU WIN 3. Block Diagram This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D MG82FE(L)308/316 Preliminary, v 0.04 8/84 ...
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... SCON SBUF P1M0 TCON TMOD 0/8 1/9 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 2/A 3/B 4/C CCAP0H -- -- -- -- -- CCAP0L -- -- IFD IFADRH IFADRL -- -- -- -- -- -- RCAP2L RCAP2H TL2 XICON1 -- -- ...
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... Program Status Word D0H GPWKPE General Port WKPE P1WKPE P1 Wakeup Enable D7H CCON Counter Control Reg. P7 Port 7 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 10/84 BIT ADDRESS AND SYMBOL Bit-7 Bit-6 Bit-5 80H P0.7 P0.6 P0 ...
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... There are two registers in Page 0 only, T2CON(C8H) and CCON(D8H), and two registers in Page F only, P6(C8H) and P7(D8H). Other registers are accessed in both page “0” and page “F”. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. ...
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... Package Instruction MG82FE(L)308AD48 (AC_MI) P1.5 (RXD1) P1.6 (TXD1) P1.7 P5.3 RST (RXD0) P3.0 (nINT2) P4.3 (TXD0) P3.1 (nINT0) P3.2 (nINT1) P3.3 (T0CKO/T0) P3.4 (T1CKO/T1) P3.5 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 12/ LQFP48 ...
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... MG82E(L)316AD64 NC (AC_MI) P1.5 (RXD1) P1.6 (TXD1) P1.7 P5.3 P5.7 RST (RXD0) P3.0 P7.6 P7.7 (nINT2) P4.3 (TXD0) P3.1 (nINT0) P3.2 (nINT1) P3.3 (T0CKO/T0) P3.4 (T1CKO/T1) P3.5 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 13/ LQFP64 ...
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... XTAL2 P6 VDD 55,56 42 VSS 23,24 18 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 14/84 TYPE I/O Port 1: General-purposed I/O Port 1. P10 T2CKO. I/O P11 is T2EX. P11 ~ P14 are the programmable comparator positive inputs. Default input is P14. ...
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... Bit 2~0: SCKS2 ~ SCKS0, programmable System Clock Selection. SCKS[2: This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 15/84 0 OSCin 1 SFR.P6.0 ℵ 2 ℵ ...
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... GPIO or clock source generator. When P60OC[1:0] index to non-P60 function, XTAL2 will drive the on-chip RC oscillator output to provide the clock source for other devices. P60OC[1: This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 16/84 Reset Value = xxx0-1010 4 3 ...
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... P6.0 output with fast driving enabled. If P6.0 is configured to clock output, enable this bit when P6.0 output frequency is more than 12MHz at 5V application or more than 6MHz at 3V application. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. ...
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... SFR Address = 0x83 SFR Page = All DPH[7] DPH[6] DPH[5] R/W R/W R Register SFR Address = 0xF0 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 18/84 Reset Value = 0000-0000 RS1 RS0 OV R/W R/W R/W Reset Value = 0000-0111 4 ...
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... Another type of indexed addressing is used in the conditional jump instruction. In conditional jump, the destination address is computed as the sum of the base pointer and the accumulator. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Fig 8-1 Program Memory 3FFFH 001BH 0013 H Interrupt Locations 000BH 0003 H Reset 0000 H This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 20/84 Program Memory 8 bytes MG82FE(L)308/316 Preliminary, v 0.04 ...
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... Fig 8-2 Lower 128 Bytes of Internal RAM Lower 128 Bytes of 30H 20H 18H Four banks of 8 10H registers R0~R7 08H 00H This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 21/84 internal SRAM 7FH 2FH Bit Addressable 1FH Bank 3 ...
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... Thus the MG82FE(L)308/316 hardware can access them correctly. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. ...
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... The MG82FE(L)308/316 has 16K bytes of on-chip code memory. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. ...
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... R/W Bit 0: DPTR select bit, used to switch between DPTR0 and DPTR1. 0: Select DPTR0. 1: Select DPTR1. DPS 0 1 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 24/84 AUXR1.DPS=0 AUXR1.DPS=1 External Data Memory Reset Value = 0000-0xx0 ...
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... When this occurs, the strong pull-up turns on for two CPU clocks, quickly pulling the port pin high. The quasi-bidirectional port configuration is shown in Figure 10-1. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Port latch data Input data 10.1.3. Input-Only (High Impedance Input) Structure The input-only configuration is a input without any pull-up resistors on the pin, as shown in Figure 10-3. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 26/84 VDD ...
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... Input Only (High Impedance Input Open-Drain Output Where x=0~4 (port number), and y=0~7 (port pin). The registers PxM0 and PxM1 are listed in each port description. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 27/84 MG82FE(L)308/316 Preliminary, v 0.04 ...
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... P1M1.5 R/W R/W R/W If any one of P1.1 ~ P1.5 is set as comparator analog input, must configure the selected I/O mode to input only to get the analog signal for comparator. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 28/84 Reset Value = 1111-1111 4 ...
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... P3M0.5 R/W R/W R/W P3M1: Port 3 Mode Register 1 SFR Address = 0xB2 SFR Page = All P3M1.7 P3M1.6 P3M1.5 R/W R/W R/W This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 29/84 Reset Value = 1111-1111 P2.4 P2.3 P2.2 R/W R/W R/W Reset Value = 0000-0000 P2M0.4 P2M0 ...
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... P5M0.5 R/W R/W R/W P5M1: Port 5 Mode Register 1 SFR Address = 0xB6 SFR Page = All P5M1.7 P5M1.6 P5M1.5 R/W R/W R/W This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 30/84 Reset Value = x111-1111 P4.4 P4.3 P4.2 R/W R/W R/W Reset Value = x000-00xx P4M0.4 P4M0 ...
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... P7.6 P7.5 R/W R/W R/W Bit 7~0: P7.7~P7.0 could be only set/cleared by CPU. Port 7 only supports one I/O mode, quasi-bidirectional mode. The register is only accessed in SFR page “F”. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 31/84 Reset Value = xxxx-xx11 ...
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... XICON0.INT3H PCON1.BOD ACON.ACF CCON.CF XICON1.IT4 nINT4 0 1 XICON1.INT4H XICON1.IT5 nINT5 0 1 XICON1.INT5H This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 32/84 Global Enable IP0L,IP0H,EIP1L,EIP1H (IE.EA) Registers IE.EX0 IE0 IE.ET0 IE.EX1 IE1 IE.ET1 IE.ES IE.ET2 XICON0 ...
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... Bit 2: IE4, External interrupt 4 Edge flag. 0: Cleared by hardware when the interrupt is starting to be serviced. It also could be cleared by CPU. 1: Set by hardware when external interrupt edge detected. It also could be set by CPU. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Enable external interrupt 2. XICON1: External Interrupt Control 1 Register SFR Address = 0xC2 SFR Page = All INT5H IT5 R R/W R/W This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 34/84 Reset Value = X000-X000 EX3 -- INT2H R/W R R/W Reset Value = X000-X000 ...
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... IP0L: Interrupt Priority 0 Low Register SFR Address = 0xB8 SFR Page = All PX3L PX2L PT2L R/W R/W R/W This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 35/84 Reset Value = XXXX-XX00 Reset Value = 0000-0000 ...
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... Bit 3: PX4H, external interrupt 4 priority-H register. Bit 2: PPTH, PWM-Timer interrupt priority-H register. Bit 1: PACH, Analog Comparator interrupt priority-H register. Bit 0: PBOH, BOD interrupt 0 priority-H register. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 36/84 ...
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... BOD interrupt is generated by BOD in PCON1, which is set by on chip Brownout-Detector meets the low voltage event. It will not be cleared by hardware when the service routine is vectored to. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... The interrupt flag was once active but not serviced is not kept in memory. Each polling cycle is new. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Timer0 and Timer1. ≅ SYSCLK 12 AUXR2.TxX12=0 AUXR2.TxX12=1 SYSCLK Tx Pin TRx GATE nINTx Pin This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 39/84 C/T=0 TLx[4:0] C/T=1 MG82FE(L)308/316 Preliminary, v 0.04 Overflow THx[7:0] TFx ...
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... Mode 2 operation is the same for Timer0 and Timer1. Ξ SYSCLK 12 AUXR2.TxX12=0 AUXR2.TxX12=1 SYSCLK Tx Pin TRx GATE nINTx Pin This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 40/84 C/T=0 TLx[7:0] C/T=1 C/T=0 TLx[7:0] C/T=1 THx[7:0] MG82FE(L)308/316 Preliminary ...
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... Timer Clock-Out Structure Ξ SYSCLK 12 AUXR2.TxX12=0 AUXR2.TxX12=1 SYSCLK C/T=0 TRx GATE=0 nINTx Pin T0/T1 Clock-out Frequency = This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 41/84 C/T=0 TL0[7:0] C/T=1 TH0[7:0] TLx[7:0] Reload THx[7:0] SYSCLK Frequency n X (256 – THx) MG82FE(L)308/316 Preliminary ...
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... Cleared when interrupt processed on if transition-activated. 1: Set by hardware when external interrupt 1 edge is detected (transmitted or level-activated). Bit 2: IT1: Interrupt 1 Type control bit. 0: Cleared by software to specify low level triggered external interrupt 1. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 42/84 ...
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... Clear to select SYSCLK/12. 1: Set to select SYSCLK as the clock source. Bit 1: T1CKOE, Timer 1 Clock Output Enable. 0: Disable Timer 1 clock output. 1: Enable Timer 1 clock output on P3.5. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 43/84 Reset Value = 0000-0000 ...
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... MEGAWIN MAKE YOU WIN Bit 0: T0CKOE, Timer 0 Clock Output Enable. 0: Disable Timer 0 clock output. 1: Enable Timer 0 clock output on P3.4. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 44/84 MG82FE(L)308/316 Preliminary, v 0.04 ...
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... Timer 2 overflow interrupt. The capture mode is illustrated in Figure 12-5. Figure 12-5 Timer 2 in Capture Mode SYSCLK 12 T2MOD.T2X12=0 T2MOD.T2X12=1 SYSCLK T2 Pin Transition Detection T2EX Pin This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 45/84 C/T2=0 TL2 (8 Bits) C/T2=1 Capture TR2 RCAP2L EXEN2 MG82FE(L)308/316 Preliminary ...
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... The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. ...
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... MEGAWIN MAKE YOU WIN Fig 12-7 Timer 2 in Auto-Reload Mode (DCEN=1) ℵ SYSCLK 12 T2MOD.T2X12=0 T2MOD.T2X12=1 SYSCLK T2 Pin This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 47/84 (Down Counting Reload Value) FFH C/T2=0 TL2 (8 Bits) (8 Bits) ...
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... Fig 12-8 Timer 2 in Baud-Rate Generator Mode ℵ SYSCLK 2 C/T2=0 C/T2=1 T2 Pin Transition Detection T2EX Pin This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 48/84 TL2 TH2 (8 Bits) (8 Bits) Reload TR2 RCAP2L RCAP2H ...
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... Disable Timer 2 clock output. 1: Enable Timer 2 clock output. Bit 0: DCEN, Timer 2 down-counting enable bit. 0: Timer 2 always keeps up-counting. 1: Enable Timer 2 down-counting ability. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 49/84 SYSCLK Frequency 4 x (65536 – ...
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... RCLK + TCLK CP/-RL2 TR2 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 50/84 Reset Value = 0000-0000 TCLK EXEN2 TR2 R/W R/W R/W DCEN T2OE x 0 (off) 0 ...
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... RCAP2H: Timer 2 Capture High Register SFR Address = 0xCB SFR Page = All RCAP2H[7] RCAP2H[6] RCAP2H[5] RCAP2H[4] RCAP2H[3] RCAP2H[2] RCAP2H[1] RCAP2H[0] R/W R/W R/W This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 51/84 Reset Value = 0000-0000 TL2[4] TL2[3] TL2[2] R/W ...
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... SYSCLK /8 /16 /32 /64 /128 IDLE CIDL CF CR PWM Output P1.x T CCAPH T CCAPH T CCAPL This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 52/84 CCAP0H CCAP0L CL 8-bit Down Counter POS2 POS1 POS0 CPS2 CR PWMEN T CCAPL T CCAPH ...
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... This flag can only be cleared by software. 1: Set by hardware when the counter rolls under. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... CACP0H: PWM Timer H-Duty Register SFR Address = 0xFA SFR Page = All CACP0H[7] CACP0H[6] CACP0H[5] CACP0H[4] CACP0H[4] CACP0H[2] CACP0H[1] CACP0H[0] R/W R/W R/W This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 54/84 Reset Value = 0000-0000 R/W R/W R/W Reset Value = 0000-0000 ...
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... REN=1. In addition to the standard operation, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... AUXR2.URM0X6 TX Clock RX Clock RXSTART REN __ RI This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 56/84 80C51 Internal BUS Write SBUF UART engine TI RI Read SBUF 80C51 Internal BUS MG82FE(L)308/316 Preliminary ...
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... P3.1/TXD D0 D1 P3.0/RXD TI RI Figure 13-5 Mode 0 Reception Waveform Write to Set REN, Clear RI SCON P3.1/TXD D0 D1 P3.0/RXD TI RI This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 57/ MG82FE(L)308/316 ...
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... This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 58/84 80C51 Internal BUS Write SBUF SM0 “ 1＂ SM1 ...
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... SM0 when SMOD0 is cleared. When SCON.7 functions as FE, it can only be cleared by firmware. Refer to Figure 13-7. Figure 13-7 UART Frame Error Detection Start D0 D1 SCON SM0/FE SM1 SM2 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 59/84 9-bit data ...
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... Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Programmed Address Note: (1) After address matching(addr_match=1), Clear SM2 to receive data bytes (2) After all data bytes have been received, Set SM2 to wait for next address. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... SM2=1 then RI will not be set unless a valid stop Bit was received, and the received byte is a Given or Broadcast address. In Mode 0, SM2 should be 0. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Given Address of all “don’t care” and a Broadcast Address of all “don’t care”. This disables the automatic address detection feature. PCON0: Power Control Register 0 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Bit 5: URM0X6, Serial Port mode 0 baud rate selector. 0: Clear to select SYSCLK/12 as the baud rate for UART Mode 0. 1: Set to select SYSCLK/2 as the baud rate for UART Mode 0. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... Timer 1 is free running, the debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 timeout period. Therefore after the initial edge event, the interrupt may occur between 1 and 2 timeout periods later. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 65/84 To ACCON ...
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... MVRS2 MVRS1 R/W R/W R/W Bit 7~4: MVRS[3:0], Minus Voltage Reference selector of analog comparator. The four bits determine the analog comparator (V-) input source as following: This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 66/84 Reset Value = 00X0-0000 4 3 ACF ...
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... Bit 1~0: PIS[3:0], Plus Voltage Reference selector of analog comparator. The two bits determine the analog comparator (V+) input source as following: PIS[2:0] (V+) Input Select 00 AC_PI0(P1.4) 01 AC_PI1(P1.3) 10 AC_PI2(P1.2) 11 AC_PI3(P1.1) This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 67/84 MVRS[3:0] (V-) Input 1000 8/16 VDD 1001 9/16 VDD 1010 10/16 VDD ...
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... WDT keeps counting while the MCU is in idle mode. Bit 2~0: PS2 ~ PS0, select prescaler output for WDT time base input. PS[2: This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 68/84 0 1/256 ...
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... MEGAWIN MAKE YOU WIN 15.3. WDT Hardware Option This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 69/ 128 256 MG82FE(L)308/316 Preliminary, v 0.04 ...
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... CPU until after the timer has reached internal counter full. The RST pin must be held high for longer than the timeout period to ensure that the device is reset properly. The device will begin executing once RST is brought low. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... SFR Page = All Bit 7~1: Reserved. Bit 0: BOD, Brown-Out Detection flag. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 71/84 Reset Value = 0001-0000 POF GF1 GF0 R/W R/W R/W Reset Value = XXXX-XXX0 ...
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... GPWKS0 P5PWM R/W R/W R/W Bit 7~6: GPWKS[1:0], Index a port with wakeup function with GPWKPE control. GPWKS[1: This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 72/84 Reset Value = 0000-0000 P14WKP P13WKP P12WKP ...
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... Others IFMT is used to select the flash mode for performing numerous This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 73/84 Reset Value = 1111-1111 4 3 R/W R/W R/W Reset Value = 0000-0000 4 3 R/W R/W R/W ...
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... Bit 4: CFAIL, Command Fail indication for ISP/IAP operation. 0: The last ISP/IAP command has finished successfully. 1: The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... ISP run over. ISP control circuit has a built-in timer for timing sequence control referred from OSC frequency and defined by CKCON2.XCKS[4:0] to get the accuracy erase/program timing. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... IAPLB and ISP start address could be defined as data flash memory and can be accessed by the ISP operation in field application. The size of IAP flash memory is variable defined by IAPLB. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. ...
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... Bit 5: P5PWM, set PWM output on P5. 0: PWM output from PWM Timer module on P2. 1: Set PWM output extend PWM output channel. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 77/84 Reset Value = 0000-0000 ...
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... Disable Timer 1 clock output. 1: Enable Timer 1 clock output on P3.5. Bit 0: T0CKOE, Timer 0 Clock Output Enable. 0: Disable Timer 0 clock output. 1: Enable Timer 0 clock output on P3.4. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 78/84 Reset Value = 000X-XX00 ...
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... This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D ...
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... DD = 3.3V, unless otherwise specified ℃ Symbol Parameter Input High voltage, V P0/P1/P2/P3/P4/P5/P6/P7 IH1 (Quasi, Input-only or Open-drain) V Input High voltage, RST IH2 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 80/84 MG82FE(L)308/316 Limits Test Condition min typ 2.0 3.5 V ...
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... Internal reset pull-down resistance RST V Comparator input common mode voltage CM V Comparator input offset voltage OS V Brown-out detection voltage BOD This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 81/84 MG82FE(L)308/316 V = VDD 0 PIN V = 0.4V ...
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... MEGAWIN MAKE YOU WIN Package Dimension 22. TQFP-64 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 82/84 MG82FE(L)308/316 Preliminary, v 0.04 ...
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... MEGAWIN MAKE YOU WIN LQFP-48 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 83/84 MG82FE(L)308/316 Preliminary, v 0.04 ...
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... MEGAWIN MAKE YOU WIN Revision History 23. Version Date V0.03 2009/Nov./16 V0.04 2010/Mar./24 This document information is the intellectual property of Megawin Technology. © Megawin Technology Co., Ltd. 2009 All rights reserved. QP-7300-03D 84/84 Page Description Initial release Modify error description 10 256B SFR 128B 9 Delete P6 24 Add LQFP-48 table ...