mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 50

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

T2CON: Timer/Counter 2 Mode Control Register
SFR Address
SFR Page
Bit 7: TF2, Timer 2 overflow flag.
0: TF2 must be cleared by software.
1: TF2 is set by a Timer 2 overflow happens. TF2 will not be set when either RCLK=1 or TCLK=1.
Bit 6: EXF2, Timer 2 external flag.
0: EXF2 must be cleared by software.
1: Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX pin and
Bit 5: RCLK, Receive clock flag.
0: Causes Timer 1 overflow to be used for the receive clock.
1: Causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3.
Bit 4: TCLK, Transmit clock flag.
0: Causes Timer 1 overflows to be used for the transmit clock.
1: Causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3.
Bit 3: EXEN2, Timer 2 external enable flag.
0: Cause Timer 2 to ignore events at T2EX pin.
1: Allows a capture or reload to occur as a result of a negative transition on T2EX pin if Timer 2 is not being used
Bit 2: TR2, Timer 2 Run control bit.
0: Stop the Timer 2.
1: Start the Timer 2.
Bit 1: C/T2, Timer or counter selector.
0: Select Timer 2 as internal timer function.
1: Select Timer 2 as external event counter (falling edge triggered).
Bit 0: CP/-RL2, Capture/Reload flag.
0: Auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX pin when EXEN2=1.
1: Captures will occur on negative transitions at T2EX pin if EXEN2=1.
When either RCLK=1 or TCLK=1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
When the DCEN is cleared, which makes the function of Timer 2 as the same as the standard 8052 (always
counts up). When DCEN is set, Timer 2 can count up or count down according to the logic level of the T2EX pin
(P1.1). The following Table shows the operation modes of Timer 2.
RCLK + TCLK CP/-RL2
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 does not cause an interrupt in up/down mode (DCEN = 1).
to clock the serial port.
TF2
R/W
7
x
1
0
0
0
0
MEGAWIN
MAKE YOU WIN
EXF2
= 0xC8
= 0
R/W
6
x
x
1
0
0
0
RCLK
TR2
R/W
0
1
1
1
1
1
5
DCEN
x
0
0
0
1
0
TCLK
R/W
4
Reset Value = 0000-0000
T2OE
0
0
0
1
0
0
EXEN2
R/W
3
(off)
Baud-rate generator
16-bit capture
16-bit auto-reload (counting-up only)
16-bit auto-reload (counting-up or counting-down)
Clock output
TR2
R/W
2
MG82FE(L)308/316
C/T2
R/W
Mode
1
Preliminary, v 0.04
CP/RL2
R/W
0