mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 37

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

IP0L, IP0H, EIP1L and EIP1H are combined to 4-level priority interrupt as the following table.
There are 13 interrupt sources available in MG82FE(L)308/316. Each interrupt source can be individually
enabled or disabled by setting or clearing a bit in the SFRs named IE, EIE1, XICON0 and XICON1. This register
also contains a global disable bit(EA), which can be cleared to disable all interrupts at once.
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPxH and
the other in IPxL register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two
interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced.
If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determine which request is serviced. The following table shows the internal polling sequence in the same priority
level and the interrupt vector address.
External interrupt 0
Timer 0
External interrupt 1
Timer1
Serial Port
Timer2
External interrupt 2
External interrupt 3
BOD
Analog Comparator
PWM Timer
External interrupt 4
External interrupt 5
The external interrupt /INT0, /INT1, /INT2, /INT3, /INT4 and INT5 can each be either level-activated or
transition-activated, depending on bits IT0 and IT1 in register TCON, IT2 and IT3 in register XICON0, IT4 and IT5
in XICON1. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON, IE2, IE3, IE4 and IE5
in XIFLG. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the
service routine is vectored to only if the interrupt was transition –activated, then the external requesting source is
what controls the request flag, rather than the on-chip hardware.
The Timer0 and Timer1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared
by the on-chip hardware when the service routine is vectored to.
The serial port interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware
when the service routine is vectored to. The service routine should poll RI and TI to determine which one to
request service and it will be cleared by software.
The timer2 interrupt is generated by the logical OR of TF2 and EXF2. Just the same as serial port, neither of
these flags is cleared by hardware when the service routine is vectored to.
BOD interrupt is generated by BOD in PCON1, which is set by on chip Brownout-Detector meets the low voltage
event. It will not be cleared by hardware when the service routine is vectored to.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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{IPH.x , IPL.x}
10
01
00
11
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Source
Priority Level
2
3
4
1 (highest)
Vector address
000BH
001BH
002BH
003BH
004BH
005BH
0003H
0013H
0023H
0033H
0043H
0053H
0063H
Priority within level
1
10
12
13
11
2
3
4
5
6
7
8
9
(highest)
MG82FE(L)308/316
Preliminary, v 0.04