mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 30

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

10.2.5. Port 4 Register
P4: Port 4 Register
SFR Address
SFR Page
Bit 6~0: P4.6~P4.0 could be only set/cleared by CPU.
P4M0: Port 4 Mode Register 0
SFR Address
SFR Page
The reset value of P4M0.1 and P4M0.0 are determined by hardware options, P41IOE and P40IOE. If the
hardware options of P41IOE and P41IOE are turned on, the reset value of P4M0.1/P4M0.0 are set to “1” to
select P4.1/P4.0 to “Input-Only” mode individually. Otherwise, the reset value of P4M0.1/P4M0.0 are cleared to
“0” to select P4.1/P4.0 to “quasi-bidirectional” mode individually.
P4M1: Port 4 Mode Register 1
SFR Address
SFR Page
10.2.6. Port 5 Register
P5: Port 5 Register
SFR Address
SFR Page
Bit 7~0: P5.7~P5.0 could be only set/cleared by CPU. P5 is also PWM output when PWM timer is enabled
running and AUXR1.P5PWM is enabled to switch PWM output from P2 to P5.
P5M0: Port 5 Mode Register 0
SFR Address
SFR Page
P5M1: Port 5 Mode Register 1
SFR Address
SFR Page
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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P5M0.7
P5M1.7
P5.7
R/W
R/W
R/W
--
--
--
7
R
7
R
7
R
7
7
7
MEGAWIN
MAKE YOU WIN
P4M0.6
P4M1.6
P5M0.6
P5M1.6
P4.6
= All
P5.6
= 0xE8
= All
= 0xB3
= 0xB4
= All
= 0xF8
= All
= 0xB5
= All
= 0xB6
= All
R/W
R/W
R/W
R/W
R/W
R/W
6
6
6
6
6
6
P4M0.5
P4M1.5
P5M0.5
P5M1.5
P4.5
P5.5
R/W
R/W
R/W
R/W
R/W
R/W
5
5
5
5
5
5
P4M0.4
P4M1.4
P5M0.4
P5M1.4
P4.4
P5.4
R/W
R/W
R/W
R/W
R/W
R/W
4
4
4
4
4
4
Reset Value = x111-1111
Reset Value = x000-00xx
Reset Value = x000-0000
Reset Value = 1111-1111
Reset Value = 0000-0000
Reset Value = 0000-0000
P4M0.3
P4M1.3
P5M0.3
P5M1.3
P4.3
P5.3
R/W
R/W
R/W
R/W
R/W
R/W
3
3
3
3
3
3
P4M0.2
P4M1.2
P5M0.2
P5M1.2
P4.2
P5.2
R/W
R/W
R/W
R/W
R/W
R/W
2
2
2
2
2
2
P4M0.1
P4M1.1
P5M0.1
P5M1.1
MG82FE(L)308/316
P4.1
P5.1
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
Preliminary, v 0.04
P4M0.0
P4M1.0
P5M0.0
P5M1.0
P4.0
P5.0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0