mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 68

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

15. Watch Dog Timer (WDT)
15.1. WDT Structure
15.2. WDT Register
WDTCR: Watch-Dog-Timer Control Register
SFR Address
SFR Page
Bit 7: WRF, WDT reset flag.
0: This bit should be cleared by software.
1: When WDT overflows, this bit is set by hardware.
Bit 6: Reserved.
Bit 5: ENW. Enable WDT.
0: ENW can not be cleared by software. It is only cleared by POR.
1: Enable WDT while it is set.
Bit 4: CLRW. Clear WDT counter.
0: Hardware will automatically clear this bit.
1: Clear WDT to recount while it is set.
Bit 3: WIDL. WDT idle control.
0: WDT stops counting while the MCU is in idle mode.
1: WDT keeps counting while the MCU is in idle mode.
Bit 2~0: PS2 ~ PS0, select prescaler output for WDT time base input.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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WRF
R/W
INT_OSC
7
PCON0.IDL
PCON0.PD
SYSCLK
NSWDT
MEGAWIN
MAKE YOU WIN
= All
= 0xE1
0 0 0
0 0 1
0 1 0
PS[2:0]
--
6
R
WDTCR Register
WRF
ENW
R/W
5
--
0
1
ENW
Prescaler Value
CLRW
CLRW
R/W
4
2
4
8
Reset Value = 0X00-XXXX
WIDL
8-bits prescaler
PS2
WIDL
1/256
1/128
R/W
1/64
1/32
1/16
1/8
1/4
1/2
3
PS1
PS0
PS2
R/W
2
MG82FE(L)308/316
15-bits WDT
PS1
R/W
1
Preliminary, v 0.04
PS0
R/W
0
WDT Reset