mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 31

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mg82fel308

Manufacturer Part Number
mg82fel308
Description
A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
Manufacturer
Megawin Technology
Datasheet
10.2.7. Port 6 Register
P6: Port 6 Register
SFR Address
SFR Page
Bit 7~2: Reserved.
Bit 1~0: P6.1~P6.0 could be only set/cleared by CPU. These two I/Os are active when Internal Oscillator is
enabled for system clock. Then, XTAL1 and XTAL2 behave P6.1 and P6.0. They only support one I/O mode,
quasi-bidirectional mode. The register is only accessed in SFR page “F”.
10.2.8. Port 7 Register
P7: Port 7 Register
SFR Address
SFR Page
Bit 7~0: P7.7~P7.0 could be only set/cleared by CPU. Port 7 only supports one I/O mode, quasi-bidirectional
mode. The register is only accessed in SFR page “F”.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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P7.7
R/W
--
7
R
7
MEGAWIN
MAKE YOU WIN
= F
P7.6
= 0xC8
= 0xD8
= F
R/W
--
6
R
6
P7.5
R/W
--
5
R
5
P7.4
R/W
--
4
R
4
Reset Value = xxxx-xx11
Reset Value = 1111-1111
P7.3
R/W
--
3
R
3
P7.2
R/W
--
2
R
2
MG82FE(L)308/316
P6.1
P7.1
R/W
R/W
1
1
Preliminary, v 0.04
P6.0
P7.0
R/W
R/W
0
0

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