mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 107

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 68:
PRECHARGE
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Data Input Timing
Notes:
1.
2.
3. Subsequent rising DQS signals must align to the clock within
4. WRITE command issued at T0.
5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
PRECHARGE can be initiated by either a manual PRECHARGE command or by an auto
precharge in conjunction with either a READ or WRITE command. PRECHARGE will
deactivate the open row in a particular bank or the open row in all banks. The
PRECHARGE operation is shown in the previous READ and WRITE operation sections.
During a manual PRECHARGE command, the A10 input determines whether one or all
banks are to be precharged. In the case where only one bank is to be precharged, bank
address inputs determine the bank to be precharged. When all banks are to be
precharged, the bank address inputs are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to
any READ or WRITE commands being issued to that bank. When a single-bank
PRECHARGE command is issued,
command is issued,
DQS, DQS#
t
t
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
CK#
DM
DQ
CK
T0
t
RPA timing applies, regardless of the number of banks opened.
WL - t DQSS (NOM)
T1
107
T1n
t
RP timing applies. When the PRECHARGE (ALL)
t
t
DQSS (MAX).
DQSS (MIN).
t WPRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
DI
t DSH 1
T2n
1Gb: x4, x8, x16 DDR2 SDRAM
t DQSL
t DSS 2
Transitioning Data
T3
3
t DQSH
t DSH 1
t
T3n
DQSS.
©2003 Micron Technology, Inc. All rights reserved.
t WPST
t DSS 2
T4
Don’t Care
Operations