mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 95

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 56:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
DQ (first data no longer valid)
DQ (first data no longer valid)
All DQs and DQS collectively 6
DQ (last data valid)
DQ (last data valid)
x4, x8 Data Output Timing –
DQS, DQS# 3
Notes:
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
CK#
Earliest signal transition
CK
Latest signal transition
1.
2.
3. DQ transitioning after the DQS transition defines the
4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.
5.
6. The data valid window is derived for each DQS transition and is defined as
T1
t
t
transitions, and ends with the last valid transition of DQ.
and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
t HP 1
t HP 1
t
t
DQSQ,
CL or
t DQSQ 2
t
HP:
t QH 5
T2
t
t
QH =
CH clock transitions collectively when a bank is active.
window
t
Data
valid
95
QH, and Data Valid Window
T2
T2
T2
t HP 1
t
HP -
t DQSQ 2
t QHS
T2n
t
t QH 5
QHS.
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t HP 1
window
T2n
T2n
Data
valid
T2n
T3
1Gb: x4, x8, x16 DDR2 SDRAM
t DQSQ 2
t QHS
t QH 5
t
DQSQ window. DQS transitions at T2
t HP 1
window
Data
valid
T3
T3
T3
T3n
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t DQSQ 2
t QHS
t HP 1
t QH 5
window
T4
t
T3n
T3n
Data
valid
T3n
QH -
Operations
t
DQSQ.
t QHS