mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 121

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 82:
MRS Command to ODT Update Delay
Figure 83:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
CKE
Applicable modes
Applicable timing parameters
Any mode except
self refresh mode
t
AOND/
Synchronous
ODT Timing for Entering and Exiting Power-Down Mode
Timing for MRS Command to ODT Update Delay
t
AOFD
Notes:
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command.
1. The LM command is directed to the mode register, which updates the information in EMR
2. To prevent any impedance glitch on the channel, the following conditions must be met:
R
Command
First CKE latched LOW
TT
Internal
setting
(A6, A2), that is, R
t
duration of the
AOFD must be met before issuing the LM command; ODT must remain LOW for the entire
ODT 2
t
ANPD (3
CK#
CK
t
CKs)
T0
Active power-down slow (asynchronous)
Precharge power-down (asynchronous)
Active power-down fast (synchronous)
t AOFD
t
Old setting
MOD window until
t
TT
AONPD/
t
AOND/
(nominal).
EMRS 1
Ta0
Synchronous or
t
Asynchronous
t
AOFPD (asynchronous)
0ns
AOFD (synchronous)
121
NOP
Ta1
t
MOD is met.
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MOD (MAX) updates the R
t MOD
Undefined
NOP
Ta2
First CKE latched HIGH
1Gb: x4, x8, x16 DDR2 SDRAM
t
AXPD (8
NOP
Ta3
t
CKs)
©2003 Micron Technology, Inc. All rights reserved.
t IS
TT
NOP
2
Ta4
setting.
Any mode except
self refresh mode
t
Synchronous
AOND/
New setting
Indicates A Break in
Time Scale
Operations
t
AOFD
NOP
Ta5