w83194br-655 Winbond Electronics Corp America, w83194br-655 Datasheet
w83194br-655
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w83194br-655 Summary of contents
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... Winbond Clock Generator W83194BR-655/W83194BG-655 For SiS 655 Chipsets Date: Feb/14/2006 Revision: 1.0 ...
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... W83194BR-655 Data Sheet Revision History PAGES DATES VERSION 1 2 n.a. 10/11/2003 3 20 12/18/03 4 2/14/2006 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... Register 15: Spread Spectrum type Control (Default: 2Ch) .................................................14 7.17 Register 16: Skew Control (Default: 24h)..............................................................................15 7.18 Register 17: Slew rate Control (Default: 00h)........................................................................15 7.19 Register 18: Slew rate Control (Default: 00h)........................................................................15 7.20 Register 19: Slew rate Control (Default: D2h) .......................................................................16 7.21 Register 20: Watch dog timer (Default: 88h).........................................................................16 7.22 Register 21: Fix Control (Default: 00h) ..................................................................................16 W83194BR-655/W83194BG-655 - II - ...
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... CPU 0.7V Electrical Characteristics ......................................................................................20 9.5 SRC 0.7V Electrical Characteristics ......................................................................................20 9.6 AGP Electrical Characteristics ...............................................................................................21 9.7 PCI Electrical Characteristics.................................................................................................21 9.8 12, 24M, 48M Electrical Characteristics ................................................................................21 9.9 REF Electrical Characteristics ...............................................................................................22 10. ORDERING INFORMATION..................................................................................................... 22 11. HOW TO READ THE TOP MARKING...................................................................................... 23 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 24 W83194BR-655/W83194BG-655 Publication Release Date: February 14, 2006 - III - Revision 1.0 ...
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... S.S.T. scale to reduce EMI. The W83194BR-655 also has watchdog timer to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-655 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • 2 pairs current mode Differential clock outputs for CPU • ...
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... CPU_STOP#*/RESET# XOUT ZCLK0 ZCLK1 VDDZ FS2*/PCI5 VDDPCI & FS3 /PCI_F0 & FS4 /PCI_F1 PCI_STOP#*/PCI0 VDDPCI #: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND W83194BR-655/W83194BG-655 GND 5 XIN 6 7 GND ...
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... P D#* Co ntro gic P CI _ST OP #* & nfig C PU_ ST OP# * Reg ister SDA ter face W83194BR-655/W83194BG-655 Divider ider I 2C Publication Release Date: February 14, 2006 - MHz MHz ...
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... PCI_F1 15 & FS4 PCI0 16 PCI_STOP#* 17,20,21,22 PCI [1:4] PCI5 12 FS2* W83194BR-655/W83194BG-655 DESCRIPTION Input Latched input at power up, internal 120kΩ pull up. Latched input at power up, internal 120kΩ pull down. Output Open Drain Active Low Internal 120kΩ pull-up Internal 120 kΩ pull-down TYPE Crystal input with internal loading capacitors (18pF) and IN feedback resistors ...
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... I C Control Interface PIN PIN NAME 34 SDATA* 35 SCLK* W83194BR-655/W83194BG-655 TYPE OUT 14.318MHz output. Latched input for FS0 at initial power up for H/W selecting IN td120k the output frequency. This is internal 120K pull down. OUT 14.318MHz output. Latched input for FS1 at initial power up for H/W selecting ...
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... VDD48 11 VDDZ 48 VDDSRC 36 VDDA 5,8,18,23,24,32, GND 37,41,45 W83194BR-655/W83194BG-655 TYPE Power good input signal is power on trapping with HIGH IN active. This 3.3V input is level sensitive strobe used to determine FS [4:0]. This pin is HIGH active. Power Down Function. This is power down pin, low active IN (PD#). tp120k Internal 120K pull up System reset signal when the watchdog is time out ...
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... W83194BR-655/W83194BG-655 SRC (MHZ) ZCLK (MHZ) 100.00 100.00 133.34 100.99 100.00 134.66 102.98 100.00 137.31 100.00 100.00 133.34 133.34 100.00 133.34 134.66 100.00 134.66 137.31 100.00 137.31 133.34 100.00 133 ...
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... Power on latched value of FS1 pin. Default: 0 (Read only Power on latched value of FS0 pin. Default: 0 (Read only) W83194BR-655/W83194BG-655 DESCRIPTION Frequency selection by software via I Enable software table selection FS [4:0 Hardware table setting (Jump mode Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output ...
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... BIT PIN NO PWD 24_48MHz output control 12_48MHz output control 48MHz output control Reserved REF1 output control REF0 output control 1 47,46 1 SRC output control Reserved W83194BR-655/W83194BG-655 DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: February 14, 2006 - 9 - Revision 1.0 ...
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... SAF_FREQ [0] 0 7.7 Register 6: Skew Control (Default: 25h) BIT NAME PWD 7 Reserved 0 Reserved 6 Reserved 0 Reserved 5 Reserved 1 Reserved 4 Reserved 0 3 Reserved 0 2 CSKEW<2> 1 CPU1 to CPU0 skew control Skew resolution is 250ps 1 CSKEW<1> 0 The decision of skew direction is same as CSKEW<2:0> setting 0 CSKEW<0> 1 W83194BR-655/W83194BG-655 DESCRIPTION DESCRIPTION - 10 - ...
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... Register 7: Winbond Chip ID (Default: 77h) (Read only) BIT NAME PWD 7 CHPI_ID [7] 0 Winbond Chip ID. W83194BR-655 (SA5877). 6 CHPI_ID [6] 1 Winbond Chip ID. 5 CHPI_ID [5] 1 Winbond Chip ID. 4 CHPI_ID [4] 1 Winbond Chip ID. 3 CHPI_ID [3] 0 Winbond Chip ID. 2 CHPI_ID [2] 1 Winbond Chip ID. ...
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... Table-2 integrate the all divider configuration 5 KVAL<5> Reserved X Reserved 3 Reserved X 2 KVAL<2> X Define the CPU divider ratio Refer to Table-2 1 KVAL<1> KVAL<0> X W83194BR-655/W83194BG-655 DESCRIPTION Programmable N divisor bit 9. Programmable N3 divisor bit 6 ~0 for programmable SRC clock. PS: Frequency range: 86.8M ~ 115.2M Resolution: 224K DESCRIPTION DESCRIPTION - 12 - ...
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... On VCO Frequency. 4 DIVM_P0 0 00: 400M 10: 667M 3 IVAL<3> X Charge pump current selection 2 IVAL<2> IVAL<1> IVAL<0> X W83194BR-655/W83194BG-655 ZCLK BIT5 1 00 Div4 Div2 Div6 Div6 DESCRIPTION VCO =14.318MHz*(N+4)/ M. frequency select SAF_FREQ [4:0] depend on Publication Release Date: February 14, 2006 - 13 - CPU BIT1 Div3 ...
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... SPSP0 1 2 ASKEW<2> ASKEW<1> ASKEW<0> 0 W83194BR-655/W83194BG-655 DESCRIPTION (2*Iref) (6*Iref => STOP mode) (2*Iref => POWER DOWN) DESCRIPTION Invert the CPU phase, 0: Default, 1: Inverse Invert the ZCLK phase, 0: Default, 1: Inverse Spread spectrum implementation method 1: Pendulum type, 0: Original Spread Spectrum type select. 00: Down ...
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... PCI_5_S1 0 5 PCI_42_S2 0 PCI4, 3,2 slew rate control 11: Strong, 00: Weak, 10/01: Normal 4 PCI_42_S1 0 3 PCI_10_S2 0 PCI1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal 2 PCI_10_S1 0 1 REF_S2 0 REF0, 1 slew rate control 11: Strong, 00: Weak, 10/01: Normal 0 REF_S1 0 W83194BR-655/W83194BG-655 DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: February 14, 2006 - 15 - Revision 1.0 ...
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... FIX_ADDR<2:0> is nonzero) 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table 5 FIX_PCI 0 PCI output frequency select mode (Only valid under FIX_ADDR<2:0> is nonzero) 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table W83194BR-655/W83194BG-655 DESCRIPTION DESCRIPTION DESCRIPTION - 16 - ...
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... Reserved for test use, don’t modify it. 2 FIX_ADDR<2> 0 Asynchronous ZCLK/AGP/PCI frequency table selection FIX_ADDR<2:0> 1 FIX_ADDR<1> FIX_ADDR<0> 0 W83194BR-655/W83194BG-655 DESCRIPTION 001: 132 / 66 / 33M 010:132 / 75.43 / 37.7M 011: 132 / 88 / 44M 100:176 / 88 / 44M 101: 132 / 66 / 33M 110:132 / 75.43 / 33M 111: 132 / 88 / 33M 000: Clock from PLL1 Publication Release Date: February 14, 2006 - 17 - ...
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... ACCESS INTERFACE The W83194BR-655 provides I W83194BR-655 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I address is defined at 0xD2. Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 8’h00 8.3 Byte Write protocol 8 ...
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... General Operating Characteristics VDD48=VDDAGP=VDDREF=VDDPCI= 3.3V PARAMETER SYMBOL Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance W83194BR-655/W83194BG-655 ± ° +70 MIN MAX UNITS V 0 ...
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... Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle 9.5 SRC 0.7V Electrical Characteristics ± VDDSRC= 3. PARAMETER Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle W83194BR-655/W83194BG-655 ± ° MIN TYP MAX UNITS 1.5 2.6 3.5 ns 150 ps 175 ps 500 ps 1000 ps ...
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... VDD48= 3. +70 PARAMETER Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max W83194BR-655/W83194BG-655 ° ° +70 C, Test load, Cl=10pF, MIN MAX UNITS 500 2000 ps 500 2000 ...
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... Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 10. ORDERING INFORMATION PART NUMBER W83194BR-655 W83194BG-655 W83194BR-655/W83194BG-655 ° ° +70 C, Test load, Cl=10pF, MIN MAX UNITS 1000 4000 ps 1000 ...
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... HOW TO READ THE TOP MARKING W83194BR-655 28051234 320GAASA 1st line: Winbond logo and the type number: W83194BR-655 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 320 G A 320: packages made in '2003, week 20 G: assembly house ID ...
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... PACKAGE DRAWING AND DIMENSIONS Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. W83194BR-655/W83194BG-655 - 24 - ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83194BR-655/W83194BG-655 Important Notice Publication Release Date: February 14, 2006 - 25 - ...