pcf2113duf4 NXP Semiconductors, pcf2113duf4 Datasheet - Page 33

• Manufacturer Part Number: pcf2113duf4
• Description: Lcd Controllers/drivers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
10 INTERFACES TO MPU
10.1
The PCF2119x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB7 to DB0. Three further control lines
E, RS and R/W are required; see Section 6.1.
In 4-bit mode data is transferred in two cycles of 4 bits
each using pads DB7 to DB4 for the transaction. The
higher order bits (corresponding to DB7 to DB4 in 8-bit
mode) are sent in the first cycle and the lower order bits
(DB3 to DB0 in 8-bit mode) in the second. Data transfer is
complete after two 4-bit data transfers. It should be noted
that two cycles are also required for the busy flag check.
4-bit operation is selected by instruction, see Figs 16 to 18
for examples of bus protocol.
In 4-bit mode, pads DB3 to DB0 must be left open-circuit.
They are pulled up to V
10.2
The I
between different ICs or modules. The two lines are the
Serial Data line (SDA) and the Serial Clock Line (SCL).
Both lines must be connected to a positive supply via
pull-up resistors. Data transfer may be initiated only when
the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus
by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte.
Also a master receiver must generate an acknowledge
after the reception of each byte that has been clocked out
of the slave transmitter.
2003 Jan 30
LCD controllers/drivers
2
C-bus is for bidirectional, two-line communication
Parallel interface
I
2
C-bus interface
SCL
SDA
TRANSMITTER/
RECEIVER
MASTER
DD
internally.
RECEIVER
SLAVE
Fig.20 System configuration.
TRANSMITTER/
RECEIVER
SLAVE
33
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration).
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
10.2.1
Before any data is transmitted on the I
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
START procedure. The I
different PCF2119x read and write cycles is shown in
Figs 24 to 26. The slow down feature of the I
protocol (receiver holds SCL LOW during internal
operations) is not used in the PCF2119x.
10.2.2
Transmitter: the device which sends the data to the bus
Receiver: the device which receives the data from the
bus
Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.
I
D
2
TRANSMITTER
C-
EFINITIONS
BUS PROTOCOL
MASTER
2
C-bus configuration for the
TRANSMITTER/
RECEIVER
MASTER
Product specification
2
PCF2119X
C-bus, the device
MGA807
2
C-bus