pcf2113duf4 NXP Semiconductors, pcf2113duf4 Datasheet - Page 8

• Manufacturer Part Number: pcf2113duf4
• Description: Lcd Controllers/drivers
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.4
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC pad must be connected to V
7.5
If an external clock is to be used this is input at the OSC
pad. The resulting display frame frequency is given by:
Only in the power-down state is the clock allowed to be
stopped (OSC connected to V
frozen in a DC state.
7.6
The PCF2119x must be reset externally. This is an internal
synchronous reset that requires 3 OSC cycles to be
executed after release of the external reset signal. If no
external reset is performed, the chip might start-up in an
unwanted state. The external reset is active HIGH.
7.7
The chip can be put into power-down mode by applying an
external active HIGH level to the PD pad. In power-down
mode all static currents are switched off (no internal
oscillator, no bias level generation and all LCD outputs are
internally connected to V
During power-down, information in the RAMs and the chip
state are preserved. Instruction execution during
power-down is possible when pad OSC is externally
clocked.
7.8
The PCF2119x has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed. The instruction register stores instruction codes
such as ‘display clear’ and ‘cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM).
Table 3 Address space and wrap-around operation
2003 Jan 30
f
Address space
Read/write wrap-around (moves to next line)
Display shift wrap-around (stays within line)
frame
LCD controllers/drivers
=
Oscillator
External clock
Power-on reset
Power-down mode
Registers
-------------
3 072
f
OSC
MODE
SS
).
SS
), otherwise the LCD is
DD
.
8
00 to 4F
4F to 00
4F to 00
1
The instruction register can be written to but not read from
by the system controller. The data register temporarily
stores data to be read from the DDRAM and CGRAM.
When reading, data from the DDRAM or CGRAM
corresponding to the address in the instruction register is
written to the data register prior to being read by the ‘read
data’ instruction.
7.9
The busy flag indicates the internal status of the
PCF2119x. A logic 1 indicates that the chip is busy and
further instructions will not be accepted. The busy flag is
output to pad DB7 when RS = 0 and R/W = 1. Instructions
should only be written after checking that the busy flag is
at logic 0 or waiting for the required number of cycles.
7.10
The address counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
commands ‘set CGRAM address’ and ‘set DDRAM
address’. After a read/write operation the address counter
is automatically incremented or decremented by 1. The
address counter contents are output to the bus
(DB6 to DB0) when RS = 0 and R/W = 1.
7.11
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic RAM to display
addressing scheme is shown in Fig.2. With no display shift
the characters represented by the codes in the first
32 RAM locations starting at address 00H in line 1 are
displayed. Figures 3 and 4 show the display mapping for
right and left shift respectively.
When data is written to or read from the DDRAM
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together. The
address ranges and wrap-around operations for the
various modes are shown in Table 3.
32
Busy flag
Address Counter (AC)
Display Data RAM (DDRAM)
00 to 27; 40 to 67
27 to 40; 67 to 00
27 to 00; 67 to 40
2
16
Product specification
PCF2119X
00 to 27
27 to 00
27 to 00
1
9