pcf2104 NXP Semiconductors, pcf2104 Datasheet - Page 22

• Manufacturer Part Number: pcf2104
• Description: Pcf2104x Lcd Controller/driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9.1
‘Clear display’ writes space code 20 (hexadecimal) into all
DDRAM addresses (the character pattern for character
code 20 must be a blank pattern), sets the DDRAM
Address Counter to logic 0 and returns the display to its
original position if it was shifted. Consequently, the display
disappears and the cursor or blink position goes to the left
edge of the display (the first line if 2 or 4 lines are
displayed) and sets the entry mode to I/D = logic 1
(increment mode). S of entry mode does not change.
The instruction ‘Clear display’ requires extra execution
time. This may be allowed for by checking the Busy Flag
(BF) or by waiting until 2 ms has elapsed. The latter must
be applied where no read-back options are foreseen, as in
some chip-on-glass (COG) applications.
9.2
‘Return home’ sets the DDRAM Address Counter to
logic 0 and returns the display to its original position if it
was shifted. DDRAM contents do not change. The cursor
or blink position goes to the left of the display (the first line
if 2 or 4 lines are displayed). I/D and S of entry mode do
not change.
9.3
9.3.1
When I/D = logic 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written to or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor and blink are inhibited
when the CGRAM is accessed.
9.3.2
When S = logic 1, the entire display shifts either to the right
(I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM
write. Consequently, it looks as if the cursor stands still and
the display moves. The display does not shift when
reading from the DDRAM, or when writing to or reading
from the CGRAM. When S = logic 0 the display does not
shift.
9.4
9.4.1
The display is on when D = logic 1 and off when
D = logic 0. Display data in the DDRAM is not affected and
can be displayed immediately by setting D to logic 1.
1997 Dec 16
LCD controller/driver
Clear display
Return home
Entry mode set
Display on/off control
I/D
S
D
22
9.4.2
The cursor is displayed when C = logic 1 and inhibited
when C = logic 0. Even if the cursor disappears, the
display functions I/D, etc. remain in operation during
display data write. The cursor is displayed using 5 dots in
the 8th line (see Fig.9).
9.4.3
The character indicated by the cursor blinks when
B = logic 1. The blink is displayed by switching between
display characters and all dots on with a period of
1 second when f
frequencies the blink period is equal to 150 kHz/f
The cursor and the blink can be set to display
simultaneously.
9.5
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2 or 4-line displays, the
cursor moves to the next line when it passes the last
position of the line (40 or 20 decimal). When the displayed
data is shifted repeatedly all lines shift at the same time;
displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the cursor shift.
9.6
9.6.1
Sets interface data width. Data is sent or received in bytes
(DB7 to DB0) when DL = logic 1 or in two nibbles
(DB7 to DB4) when DL = logic 0. When 4-bit width is
selected, data is transmitted in two cycles using the
parallel bus
Function set from I
to logic 0 from the I
to logic 0 via the parallel bus, programming via the I
interface is complicated.
9.6.2
Sets number of display lines.
(1) In a 4-bit application DB3 to DB0 are left open (internal
pull-ups). Hence in the first function set instruction after
power-on G and H are set to 1. A second function set must
then be sent (2 nibbles) to set G and H to their required
values.
Cursor/display shift
Function set
C
B
DL (
N, M
(1)
PARALLEL MODE ONLY
.
osc
2
2
C-bus interface: DL bit can not bet set
= 150 kHz (see Fig.9). At other clock
C-bus interface. If bit DL has been set
)
Product specification
PCF2104x
osc
2
C-bus
.