pcf2104 NXP Semiconductors, pcf2104 Datasheet - Page 43

• Manufacturer Part Number: pcf2104
• Description: Pcf2104x Lcd Controller/driver
• Manufacturer: NXP Semiconductors

Notes
1. X = don’t care.
2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.
STEP
17
18
19
20
21
22
23
24
25
26
(optional I
(as step 8)
Control byte:
Co = 1; RS = 0; R/W = 0; Ack = 1
Return home:
DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0;
DB1 = 1; DB0 = 0; Ack = 1
Control byte for read:
Co = 0; RS = 1; R/W = 1; Ack = 1
I
Slave address for read:
SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1;
SA0 = 0; R/W = 1; Ack = 1
Read data: 8
DB7 = X; DB6 = X; DB5 = X; DB4 = X; DB3 = X; DB2 = X;
DB1 = X; DB0 = X; Ack = 1
Read data: 8
DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0;
DB1 = 0; DB0 = 0; Ack = 0
Read data: 8
DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0;
DB1 = 0; DB0 = 1; Ack = 1
I
2
2
C-bus start
C stop
2
C-bus stop) I
SCL + master acknowledge; note 2:
SCL + master acknowledge; note 2:
SCL + no master acknowledge; note 2:
I
2
2
C-BUS BYTE
C-bus start + slave address for write
PHILIPS_
PHILIPS_
PHILIPS
PHILIPS
PHILIPS
PHILIPS
PHILIPS
PHILIPS
PHILIPS
PHILIPS
DISPLAY
Sets DDRAM address 0 in Address Counter. (Also returns
shifted display to original position. DDRAM contents
unchanged). This instruction does not update the Data
Register (DR).
DDRAM content will be read from following instructions.
The R/W has to be set to 1 while still in I
mode.
During the acknowledge cycle the content of the DR is
loaded into the internal I
In the previous instruction neither a ‘Set address’ nor a
‘Read data’ has been performed. Therefore the content of
the DR was unknown.
8
acknowledge cycle is shifted out over SDA. MSB is DB7.
During master acknowledge content of DDRAM
address 01 is loaded into the I
8
acknowledge code of ‘I’ is loaded into the I
interface.
No master acknowledge; After the content of the I
interface register is shifted out no internal action is
performed. No new data is loaded to the interface register,
Data Register (DR) is not updated, Address Counter (AC)
is not incremented and cursor is not shifted.
SCL; content loaded into interface during previous
SCL; code of letter ‘H’ is read first. During master
OPERATION
2
C-bus interface to be shifted out.
2
C-bus interface.
2
C-bus write
2
C-bus
2
C-bus