pca8576d NXP Semiconductors, pca8576d Datasheet - Page 19

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pca8576d

Manufacturer Part Number
pca8576d
Description
Automotive 40 X 4 Lcd Segment Driver For Low Multiplex Rates Up To 1 4
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
PCA8576D
Product data sheet
7.16.1 Bit transfer
7.16 Characteristics of the I
In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of
LCD segments can blink selectively by changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the nominal blink frequency by
sequentially resetting and setting the display enable bit E at the required rate using the
mode-set command (see
Table 6.
[1]
The I
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Blink mode
off
1
2
3
Fig 12. Bit transfer
Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator
frequency (f
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
Blinking frequencies
clk
) of 1536 Hz (see
All information provided in this document is subject to legal disclaimers.
SDA
SCL
Automotive 40 x 4 LCD segment driver for low multiplex rates
Rev. 1 — 4 April 2011
Table
Normal operating mode ratio
-
--------- -
768
------------ -
1536
------------ -
3072
f
f
f
clk
clk
clk
2
Section
C-bus
[1]
10).
data valid
data line
stable;
11).
Figure
allowed
change
of data
12).
Nominal blink frequency
blinking off
2 Hz
1 Hz
0.5 Hz
PCA8576D
mba607
© NXP B.V. 2011. All rights reserved.
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