pca85232 NXP Semiconductors, pca85232 Datasheet
pca85232
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pca85232 Summary of contents
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... LCD driver for low multiplex rates Rev. 1 — 8 December 2010 1. General description The PCA85232 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and up to 160 segments. It can be easily cascaded for larger LCD applications. The PCA85232 is compatible with most ...
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... Marking codes All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Delivery form chips with bumps in tray PCA85232U Marking code PC85132/232-1 © NXP B.V. 2010. All rights reserved. Version ...
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... LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCA85232 PCA85232 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCA85232 BLINKER TIMEBASE COMMAND POWER-ON ...
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... Pinning information 6.1 Pinning PCA85232 Viewed from active side. For mechanical details, see Fig 2. Pinning diagram of PCA85232 + Figure 32. 013aaa283 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Description 2 I C-bus acknowledge output 2 I C-bus serial data input ...
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... LCD segment or dot matrix displays (see Figure backplanes and up to 160 segments. The display configurations possible with the PCA85232 depend on the required number of active backplane outputs. A selection of display configurations is given in All of the display configurations given in as shown in Fig 3 ...
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... The internal oscillator is selected by connecting pin OSC to V power supplies (V 7.1 Power-On Reset (POR) At power-on the PCA85232 resets to the following starting conditions: • All backplane and segment outputs are set to V • The selected drive mode is 1:4 multiplex with • ...
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... LCD off(RMS) > LCD th ⁄ 1 bias are possible but the discrimination and and is determined from off(RMS) PCA85232 RMS D = ------------------------ - off RMS ∞ 2.236 2.236 1.915 1.732 Equation 1: (1) Equation ...
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... Equation 1 to Equation 3) and the V are properties of the LCD liquid and can be provided by the module high All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates × 2.449V ( ) ( ...
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... PCA85232 Product data sheet 100 % OFF SEGMENT Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates V [V] V RMS low high GREY ON SEGMENT SEGMENT 001aam358 © ...
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... V (t). state2 (Sn+1) BP0 off(RMS) Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) 013aaa207 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7.4.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA85232 allows the use of Figure 8. Fig 7. PCA85232 Product data sheet ⁄ bias LCD V /2 BP0 LCD LCD BP1 V /2 LCD V SS ...
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... BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms 013aaa209 at LCD segment. ⁄ ...
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... BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms 013aaa210 at LCD segment. ⁄ ...
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... V ( (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates T fr state 1 state 2 013aaa211 at LCD segment. ⁄ 1 bias 3 LCD segments © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCA85232 are timed by a frequency f which either is derived from the built-in oscillator frequency f clk f = clk or equals an external clock frequency clk Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD state, which is not suitable for the liquid crystal ...
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... BP1, BP2, and BP3 respectively. PCA85232 Product data sheet Figure 11, shows the rows which correspond with the All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors Fig 11. Display RAM bitmap When display data is transmitted to the PCA85232 the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCA85232 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character ...
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... NXP Semiconductors The PCA85232 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled ...
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... NXP Semiconductors By connecting pin SDAACK to pin SDA on the PCA85232, the SDA line becomes fully 2 I C-bus compatible. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be significant, possibly a voltage divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance consequence it may be possible that the acknowledge generated by the PCA85232 can’ ...
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... SCL from 1 master S START condition 2 C-bus All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER Figure 16. not acknowledge acknowledge 2 8 clock pulse for ...
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... Bit The PCA85232 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCA85232 will respond to, is defined by the level tied to its SA0 input (V Having two reserved slave addresses allows the following on the same I • ...
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... In this way it is possible to configure the device and then fill the display RAM with little overhead. The command bytes and control bytes are also acknowledged by all addressed PCA85232 connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter; see ...
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... NXP Semiconductors The acknowledgement after each byte is made only by the (A0 and A1) addressed PCA85232. After the last (display) byte, the I Alternatively a START may be asserted to RESTART an I 7.17 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCA85232 are defined in Table 9 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Table [1] 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 [2] [3] © NXP B.V. 2010. All rights reserved. ...
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... Power-on and reset value. 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCA85232 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. ...
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... SYNC, T1, T2, A0, A1, OSC, CLK, SA0 V SS All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates SDAACK, SCL, SDA, T3, V LCD V SS 013aaa221 © NXP B.V. 2010. All rights reserved. ...
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... Ref. 8 “JESD78” °C). All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD ...
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... pin OSC CLK, A0, A1, SA0, SDA, and SCL All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates ° +95 C; unless otherwise specified. Min Typ 1.8 - 1.8 - [1][2][3] - ...
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... V; all RAM written with logic 1; no display connected. amb LCD with respect All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates ° +95 C; unless otherwise specified. Min Typ −30 ...
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... RAM written with logic 1; no display connected amb f = 3.500 kHz. clk(ext) with respect to V DD(LCD) LCD All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates 001aal526 (V) LCD clk © NXP B.V. 2010. All rights reserved. ...
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... SDA and SCL signals of both SDA and SCL signals see Table 16 All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates ° +95 C; unless otherwise specified. Min [1][2][3] 3050 3500 4052 Hz [4] ...
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... V ± 0.5 V; frame frequency prescaler = 011; 146 Hz typical. Condition The frame frequency ( calculated from the clock frequency (f fr described in Table 16. All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates 001aal527 ( max 5 ...
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... HD;DAT LOW SCL t VD;ACK t t HD;STA All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates CLK t clk(L) t VD;ACK t HIGH clock t BUF t SU;STO clock ...
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... OL = ------------------------- - ) I OL are shown in Figure 26 and All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates ) is defined between the 0.7V . The value for t DD r(max and the bus capacitance (C r due to the specified minimum ...
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... PU(min) 2 C-bus acknowledge line (SDAACK) are split. Both SDA SDAACK two wire mode All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates 001aak441 260 300 340 380 420 460 C b 001aak440 3 ...
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... PCA85232 with different SA0 levels are cascaded). SYNC is organized as an input/output pin; the output selection being realized as an open-drain driver with an internal pull-up resistor. A PCA85232 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCA85232 to assert SYNC ...
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... In the cascaded applications, the OSC pin of the PCA85232 with subaddress 0 is connected to V the CLK pin. The other PCA85232 devices are having the OSC pin connected to V meaning that these devices are ready to receive external clock, the signal being provided by the device with subaddress 0. ...
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... V LCD V DD MICRO- PROCESSOR/ MICRO- CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 29. Cascaded configuration with two PCA85232 using the internal clock of the master PCA85232 Product data sheet SDA SCL SYNC CLK OSC t r ≤ ...
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... NXP Semiconductors V LCD V DD PROCESSOR/ CONTROLLER V SS (1) Is master (OSC connected to V (2) Is slave (OSC connected to V Fig 30. Cascaded configuration with one PCA85232 and one PCA85133 using the internal PCA85232 Product data sheet SYNC t r ≤ SDA HOST MICRO- SCL ...
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... NXP Semiconductors Fig 31. Synchronization of the cascade for the various PCA85232 drive modes PCA85232 Product data sheet = BP0 SYNC (a) static drive mode BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1:2 multiplex drive mode BP2 (1/3 bias) SYNC (c) 1:3 multiplex drive mode BP3 (1/3 bias) SYNC (d) 1:4 multiplex drive mode All information provided in this document is subject to legal disclaimers. Rev. 1 — ...
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... Unit max 0.018 mm nom 0.40 0.015 0.380 0.0338 min 0.012 Note 1. Dimension not drawn to scale. Outline version IEC PCA85232U Fig 32. Bare die outline of PCA85232 PCA85232 Product data sheet 197 detail scale (1) (1) (1) ( ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Symbol Bump X (μm) S68 100 750.2 S69 101 696.2 S70 102 642.2 S71 103 588 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Symbol Bump X (μm) −1494.2 S103 139 −1548.2 S104 140 −1602.2 S105 141 −1656.2 ...
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... S130 Table Alignment marking Figure 32. Size (μm) 121.5 × 121.5 121.5 × 121.5 All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Symbol Bump X (μm) −2431.2 S142 178 −2377.2 S143 179 − ...
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... NXP Semiconductors Fig 33. Alignment marks PCA85232 Product data sheet REF S1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates REF C1 001aah849 © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates Value 8.8 mm 3.6 mm 6.65 mm 1.31 mm 50 ...
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... Random Access Memory Root Mean Square Serial CLock line Serial DAta line All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates marking code 001aaj643 © NXP B.V. 2010. All rights reserved ...
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... Devices [10] NX3-00092 — NXP store and transport requirements [11] UM10204 — I 17. Revision history Table 27. Revision history Document ID Release date PCA85232 v.1 20101208 PCA85232 Product data sheet 2 C-bus specification and user manual Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. ...
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... All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 December 2010 PCA85232 LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... Max value of pull-up resistor . . . . . . . . . . . . . 37 Min value of pull-up resistor . . . . . . . . . . . . . . 37 SDA and SDAACK configuration . . . . . . . . . . 38 Cascaded operation Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 44 Packing information . . . . . . . . . . . . . . . . . . . . 49 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 50 References Revision history . . . . . . . . . . . . . . . . . . . . . . . 51 Legal information . . . . . . . . . . . . . . . . . . . . . . 52 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 52 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Contact information . . . . . . . . . . . . . . . . . . . . 53 Contents Date of release: 8 December 2010 Document identifier: PCA85232 All rights reserved. ...