pca85232 NXP Semiconductors, pca85232 Datasheet - Page 16

• Manufacturer Part Number: pca85232
• Description: Pca85232 Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA85232
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing and frame frequency
7.7 Display register
The internal logic and the LCD drive signals of the PCA85232 are timed by a frequency
f
or equals an external clock frequency f
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
The internal oscillator is enabled by connecting pin OSC to V
from pin CLK provides the clock signal for cascaded PCA85232 in the system. However,
the clock signal is only available at pin CLK, if the display is enabled. The display is
enabled using the display enable bit (see
The output clock frequency is like specified in
Connecting pin OSC to V
external clock input.
The timing of the PCA85232 organizes the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCA85232 in the system.
When the internal clock is used, the clock frequency can be programmed by software
such that the frame frequency can be chosen in the range of 117 Hz to 176 Hz (see
Table
V
The timing also generates the LCD frame frequency derived from an integer division of f
(see
The display register holds the display data while the corresponding multiplex signals are
generated.
clk
DD
f
f
clk
clk
which either is derived from the built-in oscillator frequency f
= 5.0 V; T
Table
16). The internal oscillator is calibrated within an accuracy of ±5.1 % (at
=
=
f
------- -
f
64
osc
clk ext
16).
(
amb
)
All information provided in this document is subject to legal disclaimers.
= 30 °C).
Rev. 1 — 8 December 2010
DD
enables an external clock source. Pin CLK then becomes the
clk(ext)
Table
:
Table 19
10).
LCD driver for low multiplex rates
with parameter f
SS
. In this case the output
osc
:
PCA85232
© NXP B.V. 2010. All rights reserved.
clk
.
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(6)
(7)
clk