m41t93 STMicroelectronics, m41t93 Datasheet
m41t93
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m41t93 Summary of contents
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... M41T93S 3.0V to 5.5V CC (2.85V V 3.00V) RST – M41T93R 2.7V to 5.5V CC (2.55V V 2.70V) RST – M41T93Z 2.38V to 5.50V CC (2.25V V 2.38V) RST ■ Compatible with SPI bus serial interface (positive clock SPI modes) ■ Programmable alarm with interrupt function (valid even during battery back-up mode) nd ■ ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M41T93 is a low power Serial SPI Bus Real Time Clock with a built-in 32.768kHz oscillator (external crystal-controlled for the QFN16 package, and embedded crystal for the SOX18 package). Eight bytes of the Register Map (see clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 17 bytes of the Register Map provide status/control of the two Alarms, Watchdog, 8-Bit Counter, and Square Wave functions ...
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Figure 1. Logic diagram XI (1) XO (1) SDI SCL E 1. For QFN16 package only. 2. Defaults to 32kHz on power-up. 3. Open drain Table 1. Signal name Symbol (1) XI 32kHz oscillator input (1) XO 32kHz oscillator output ...
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... SQW ( ( ( RST M41T93 E ( SDO ( SQW IRQ/FT/OUT V BAT 8 11 SCL SDI . Pins 2 and 3, and 16 and 17 are internally shorted together SDO (1) IRQ/FT/OUT ...
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Figure 4. Block diagram XI CRYSTAL XO E SDI SCL SDO BAT (2) V RST / Open drain output 2.93V (S), 2.63V (R), and 2.32V (Z). RST SO REAL TIME ...
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... Figure 5. Hardware hookup V CC M41T93 V CC IRQ/FT/OUT BAT Open drain output 2. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU. Table 2. Function table Mode E Disable Reset H WRITE L READ L 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ. ...
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... The output data on the SDO pin changes state after the falling edge of the clock input. The M41T93 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: (CPOL, CPHA) = ('0', '0'), or (CPOL, CPHA) = ('1', '1') ...
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... Operation The M41T93 clock operates as a slave device on the SPI serial bus. Each memory device is accessed by a simple serial interface that is SPI bus-compatible. The bus signals are SCL, SDI, and SDO (see when the Chip Enable input (E) is held low. All instructions, addresses and data are shifted serially in and out of the chip ...
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... The SCL input, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus (see The M41T93 can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: (CPOL, CPHA) = ('0', '0'), or (CPOL, CPHA) = ('1', '1') ...
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Figure 7. Read mode sequence SCL W/R BIT 7 BIT ADDRESS SDI MSB SDO HIGH IMPEDANCE Figure 8. Write mode sequence SCL 7 BIT ADDR W/R ...
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... When it is powered back up, the device switches back from battery to V hysteresis. When V on Battery Storage Life refer to Application Note AN1012. 2.4 Power-on reset (t The M41T93 continuously monitors V the RST output pulls low (open drain) and remains low after power-up for t typical) after V rises above V CC ...
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... Clock operation The M41T93 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768kHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see the date and time from the clock, in binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers ...
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... Clock/control register map The M41T93 offers 32 internal registers which contain Clock, Calibration (Digital and Analog), Alarm 1 and 2, Watchdog, Flags, Timer, and Square Wave. The Clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORT™ TIMEKEEPER independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy ...
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Table 3. Clock/control register map (32 bytes) Addr 00h 0.1 Seconds 01h ST 10 Seconds 02h 0 10 Minutes 03h CB1 CB0 10 Hours 04h 05h Date 06h ...
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... Real time clock accuracy The M41T93 is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The accuracy of the Real Time Clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Temperature also affects the crystal frequency, ...
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... Clock calibration The M41T93 oscillator is designed for use with a 12.5pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than ±1 ppm at 25°C. The M41T93 design provides the following two methods for clock error correction. 3.4.1 Digital calibration (periodic counter correction) This method employs the use of periodic counter correction by adjusting the ratio of the 100Hz divider stage to the 512Hz divider stage ...
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Table 4. Digital calibration values Calibration value (binary) DC4 – DC0 0 (00000) 1 (00001) 2 (00010) 3 (00011) 4 (00100) 5 (00101) 6 (00110) 7 (00111) 8 (01000) 9 (01001) 10 (01010) 11 (01011) 12 (01100) 13 (01101) 14 ...
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Analog calibration (programmable load capacitance) A second method of calibration employs the use of programmable internal load capacitors to adjust (or trim) the oscillator frequency. By design, the oscillator is intended ppm ± crystal accuracy at ...
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Figure 10. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 –20 Table 5. Analog calibration values Analog Calibration D7 D6 Value Addr ACS AC6 (±) (16pF) 0pF x 0 3pF ...
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... The combination of analog and digital trimming can give up to –93 to +156 ppm of the total adjustment. Figure 11 on page 25 Calibration value. This curve may vary with different crystals good practice to evaluate the crystal to be used with an M41T93 device before establishing the adjustment values for the application in question. 24/51 AC6 AC0 value – ...
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Figure 11. Clock accuracy vs. on-chip load capacitors 100.0 80.0 60.0 40.0 20.0 FASTER 0.0 SLOWER -20.0 OFFSET TO -18.0 -15 (pF NET EQUIV. LOAD CAP (pF) LOAD Analog Calibration 0xC8 0xBC Value, ...
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... Two methods are available for ascertaining how much calibration a given M41T93 may require: ● The first involves setting the clock, letting it run for a month and comparing known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure ...
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Figure 13. Crystal isolation example Note: The substrate pad should be tied to V 3.5 Setting the alarm clock registers Address locations 0Ah-0Eh (Alarm 1) and 14h-18h (Alarm 2) contain the alarm settings. Either alarm can be configured independently to ...
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Optional second programmable alarm When the Alarm 2 Enable (AL2E) Bit (D1 of address 13h) is set to a logic ‘1,’ registers 14h through 18h provide control for a second programmable alarm which operates in the same manner as ...
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... At the end of every countdown, the timer sets the Timer Flag (TF) Bit. The TF Bit can only be cleared by software. When asserted, the timer flag (TF) can also be used to generate an interrupt (IRQ/FT/OUT) on the M41T93. The interrupt may be generated as a pulsed signal every countdown period permanently active signal which follows the condition of TF ...
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TI/TP ● TI/ IRQ/FT/OUT is active when TF is logic '1' (subject to the status of the Timer Interrupt Enable Bit (TIE). ● TI/ IRQ/FT/OUT pulses active according to Note alarm condition, watchdog ...
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TD1/0 These are the timer source clock frequency selection bits (see determine the source clock for the countdown timer (see TD1 and TD0 Bits should be set to ‘11’ (1/60Hz) for power saving. Table 9. Timer source clock frequency ...
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... Square wave output The M41T93 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 4. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah ...
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... Battery low warning The M41T93 automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval ...
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... The ST Bit is set to '1.' ● External interference of the crystal For the M41T93, if the Oscillator Fail Interrupt Enable Bit (OFIE) is set to a '1,' the IRQ/FT/OUT pin will also be activated. The IRQ/FT/OUT output is cleared by resetting the OFIE or OF Bit to '0' (NOT by reading the Flag Register). ...
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Initial power-on defaults Upon initial application of power to the device, the register bits will initially power-on in the state indicated in Table 13 Table 13. Initial power-on default values (part 1) (1) Condition ST CB1 CB0 OUT FT ...
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... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 15. ...
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... C OUT 1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested 25° 1MHz. 3. Outputs deselected. Parameter ) ) A , typical) L 0.8V CC 0.2V CC (1)(2) Parameter Input capacitance Output capacitance M41T93 2.38V to 5.5V –40 to +85°C 30pF 50ns 0. 0. 0.7V CC 0.3V CC AI02568 Min Max Unit 7 ...
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Table 18. DC characteristics Sym Parameter Operating voltage (S) V Operating voltage (R) CC Operating voltage (Z) I Input leakage current LI I Output leakage current LO Supply current I SCL = 0.1V /0.9V CC1 CC CC SDO = Open ...
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... MS3V-T1R (1.5x5mm) for surface-mount, tuning fork-type quartz crystals. For contact information, see Section 8: References on page 49. 2. Load capacitors are integrated within the M41T93. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design. ...
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Figure 18. Power down/up mode AC waveforms tPD SCL SDI Table 21. Power down/up trip points DC characteristics Sym V Reset threshold voltage RST Battery back-up switchover V SO Hysteresis Reset pulse Width ( ...
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Figure 19. Input timing requirements E tCHEL SCL tDVCH MSB IN SDI HIGH IMPEDANCE SDO Figure 20. Output timing requirements E SCL tCLQV tCLQX MSB OUT SDO ADDR. LSB IN SDI tELCH tCHEH tCHDX tCLCH tDLDH tDHDL tCH tEHEL tEHCH ...
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Table 22. AC characteristics Sym f SCL clock frequency SCL t E Active setup time ELCH t E Not active setup time EHCH t E Deselect time EHEL t E Active hold time CHEH t E Not active hold time ...
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Package mechanical information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the ...
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Figure 21. QFN16 – 16-lead, quad, flat package, no lead, 4x4mm body size, outline 1. Drawing is not to scale. 2. Substrate pad should be tied to V 44/ ddd ( ...
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Table 23. QFN16 – 16-lead, quad, flat package, no lead, 4x4mm body, mech. data mm Sym Typ Min A 0.90 0.80 A1 0.02 0.00 A3 0.20 b 0.30 0.25 D 4.00 3.90 D2 – 2.50 E 4.00 3.90 E2 – ...
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Figure 22. QFN16 – 16-lead, quad, flat, no lead, 4x4mm, recommended footprint 1. Dimensions shown are in millimeters (mm). 2. Substrate pad should be tied to V Figure 23. 32kHz crystal + QFN16 vs. VSOJ20 mechanical data Note: Dimensions shown ...
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Figure 24. SOX18 – 18-lead plastic small outline, 300mils, embedded crystal A2 B SO-J Note: Drawing is not to scale. Table 24. SOX18 – 18-lead plastic SO, 300mils, embedded crystal, pkg. mech. data Sym Typ ...
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Part numbering Table 25. Ordering information Example: Device family M41T Device type 93 Operating voltage 3. 2. 2.38 to 5.5V CC ...
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References Below is a listing of the crystal component suppliers mentioned in this document. ● KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. ● Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. ● Micro Crystal can be contacted at ...
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Revision history Table 26. Document revision history Date Revision 07-Aug-2006 08-May-2007 22-Oct-2007 50/51 1 Initial release. Document status upgraded to full datasheet; updated Clock accuracy vs. on-chip load 2 Section 3.4.1; Table 1, 15, and 18, I vs. temperature. ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...