m41t93 STMicroelectronics, m41t93 Datasheet - Page 11

no-image

m41t93

Manufacturer Part Number
m41t93
Description
Serial Spi Bus Rtc With Battery Switchover
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
m41t935MY6
Manufacturer:
ST
0
Part Number:
m41t93RMV6
Manufacturer:
ST
Quantity:
20 000
Part Number:
m41t93RMY6
Manufacturer:
ST
Quantity:
8 000
Part Number:
m41t93RMY6
Manufacturer:
ST
0
Part Number:
m41t93RMY6
Manufacturer:
ST
Quantity:
20 000
Part Number:
m41t93RMY6F
Manufacturer:
NSC
Quantity:
456
Part Number:
m41t93RMY6F
Manufacturer:
ST
0
Part Number:
m41t93RMY6F
Quantity:
55
Part Number:
m41t93RQA6F
Manufacturer:
ST
Quantity:
2 403
Part Number:
m41t93RQA6F
Manufacturer:
ST
0
Part Number:
m41t93S
Manufacturer:
ST
Quantity:
20 000
Part Number:
m41t93SMY6F
Manufacturer:
ST
Quantity:
1 964
Part Number:
m41t93SQA6F
Manufacturer:
STMicroelectronics
Quantity:
1 934
Part Number:
m41t93SQA6F
Manufacturer:
ST
Quantity:
842
Part Number:
m41t93ZMY6
Manufacturer:
ST
Quantity:
20 000
1.1
1.1.1
1.1.2
1.1.3
1.1.4
SPI signal description
Serial data output (SDO)
The output pin is used to transfer data serially out of the Memory. Data is shifted out on the
falling edge of the serial clock.
Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and
the data to be written, are each received this way. Input is latched on the rising edge of the
serial clock.
Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in
page 41
input pin, on the rising edge of the clock input. The output data on the SDO pin changes
state after the falling edge of the clock input.
The M41T93 can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0'), or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock
SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see
on page 10
Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high
impedance state.
After power-on, a high-to-low transition on E is required prior to the start of any operation.
and
and <Blue>Figure 6., page 10).
Figure 20 on page
41). The W/R Bit, addresses, or data are latched, from the
Figure 19 on
Table 2
11/51

Related parts for m41t93