hi5767 Intersil Corporation, hi5767 Datasheet
hi5767
Available stocks
Related parts for hi5767
hi5767 Summary of contents
Page 1
... The 250MHz Full Power Input Bandwidth and superior high frequency performance of the HI5767 converter make it an excellent choice for implementing Digital IF architectures in communications applications. The HI5767 has excellent dynamic performance while consuming only 310mW power at 40MSPS ...
Page 2
... HI5767/2CAZ SSOP (See Note) (Pb-free) HI5767/2IA - SSOP HI5767/2IAZ - SSOP (See Note) (Pb-free) HI5767/4CA SSOP HI5767/4CAZ SSOP (See Note) (Pb-free) HI5767/6CA SSOP HI5767/6CAZ SSOP (See Note) (Pb-free) HI5767EVAL1 ...
Page 3
... Functional Block Diagram S/H + ∑ ∑ HI5767 BIAS STAGE 1 2-BIT 2-BIT FLASH DAC STAGE 8 2-BIT 2-BIT FLASH DAC STAGE 9 2-BIT FLASH AV AGND DV DGND1 CC CC1 CLK CLOCK V REFOUT REFERENCE V REFIN DFS OE DV CC2 D9 (MSB DIGITAL DELAY D5 AND DIGITAL ERROR ...
Page 4
... V - Negative Analog Input Bias Voltage Output DC 12 AGND Analog Ground 13 AV Analog Supply (+5.0V Digital Output Enable Control Input 4 HI5767 HI5767 V (7) REFIN V (8) REFOUT (LSB) (28 (27 (26) D2 AGND (12) D2 AGND (6) (25 DGND (24 DGND1 (2) ...
Page 5
... Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV Operating Conditions Temperature Range HI5767/xCx HI5767/xIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
Page 6
... Harmonic Distortion HI5767/2 HI5767/4 HI5767/6 3rd Harmonic Distortion HI5767/2 HI5767/4 HI5767/6 Spurious Free Dynamic Range, SFDR HI5767/2 HI5767/4 HI5767/6 Intermodulation Distortion, IMD Differential Gain Error Differential Phase Error Transient Response Over-Voltage Recovery ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input ...
Page 7
... Supply Current Power Dissipation Offset Error Sensitivity, ∆V OS Gain Error Sensitivity, ∆FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock low and DC input. 7 HI5767 = DV = 5.0V 3.0V CC1 CC2 REFIN Differential Analog Input; Typical Values are Test Results at 25 ...
Page 8
... SINAD vs SAMPLING FREQUENCY 1MHz 10MHz 15MHz SAMPLING FREQUENCY (MSPS) FIGURE 4. -THD vs SAMPLING FREQUENCY 8 HI5767 1. 2.4V DATA N-1 0.5V FIGURE 1. INPUT TO OUTPUT TIMING 5MHz ...
Page 9
... S FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK FREQUENCY 2.530 2.525 V REFOUT 2.520 2.515 2.510 -40 - TEMPERATURE ( FIGURE 10. INTERNAL REFERENCE VOLTAGE (V TEMPERATURE 9 HI5767 (Continued) 9.1 9.0 8.9 8.8 8.7 8.6 8.5 8.4 8 0.25 0. CLK FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB 9.0 AI 8.8 CC 8.6 8.4 DI CC1 8 ...
Page 10
... OD 0 -10 -20 - -50 -60 -70 -80 -90 -100 0 100 200 300 400 500 600 FREQUENCY (BIN) FIGURE 14. 2048 POINT FFT PLOT 10 HI5767 (Continued TEMPERATURE = 60MSPS 10MHz IN 700 800 900 1023 ...
Page 11
... The voltages listed above represent the ideal center of each output code shown with V Detailed Description Theory of Operation The HI5767 is a 10-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 16 depicts the circuit for the front end differential-in-differential-out sample- and-hold (S/H). The switches are controlled by an internal sampling clock which is a non-overlapping two phase signal, Φ ...
Page 12
... V Analog Input, Differential Connection The analog input to the HI5767 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 17 and Figure 18) will deliver the best performance from the converter ...
Page 13
... Digital Output Control and Clock Requirements The HI5767 provides a standard high-speed interface to external TTL logic families. In order to ensure rated performance of the HI5767, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL levels. ...
Page 14
... RMS amplitude of the next largest spectral component in the spectrum below f / HI5767 Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the ...
Page 15
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 HI5767 Data Hold Time ( Data hold time is the time to where the previous data ( longer valid ...