uda1355h-n2 NXP Semiconductors, uda1355h-n2 Datasheet - Page 32

• Manufacturer Part Number: uda1355h-n2
• Description: Stereo Audio Codec With Spdif Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 15 Preambles
9.3
9.3.1
The SPDIF specification IEC 60958 supports three levels
of clock accuracy:
The UDA1355H inputs support level I, II, and III as
specified by the IEC 60958 standard.
9.3.2
Rise and fall times (see Fig.14) are defined as:
Rise time =
Fall time =
Rise and fall times should be in the range:
2003 Apr 10
handbook, halfpage
Level I high accuracy: Tolerance of transmitting
sampling frequency shall be within 50
Level II, normal accuracy: All receivers should receive a
signal of 1000
Level III, variable pitch shifted clock mode: A deviation
of 12.5% of the nominal sampling frequency is possible.
0% to 20% when the data bit is a logic 1
0% to 10% when the data bits are two succeeding
logic 0.
Stereo audio codec with SPDIF interface
PRECEDING
STATE
Timing characteristics
W
M
B
F
R
90%
50%
10%
REQUENCY REQUIREMENTS
Fig.14 Rise, fall time and duty cycle.
ISE AND FALL TIMES
---------------
t
L
---------------
t
L
+
t
+
f
t
r
t
H
t
H
t r
10
100%
100%
6
t H
11101000
11100010
11100100
of nominal sampling frequency
CHANNEL CODING
0
t f
t L
10
MGU612
00010111
00011101
00011011
6
1
32
9.3.3
The duty cycle (see Fig.14) is defined as:
Duty cycle =
The duty cycle should be in the range:
10 L3-BUS DESCRIPTION
The exchange of data and control information between the
microcontroller and the UDA1355H is accomplished
through a serial hardware L3-bus interface comprising the
following pins:
The exchange of bytes in L3-bus mode is LSB first.
The L3-bus format has two modes of operation:
The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see
Fig.15). The data transfer mode is characterized by
L3MODE being HIGH and is used to transfer one or more
bytes representing a register address, instruction or data.
Basically two types of data transfers can be defined:
10.1
The device address consists of one byte with:
40% to 60% when the data bit is a logic 1
45% to 55% when the data bits are two succeeding
logic 0.
MP0: mode line with signal L3MODE
MP1: clock line with signal L3CLOCK
MP2: data line with signal L3DATA.
Address mode
Data transfer mode.
Write action: data transfer to the device
Read action: data transfer from the device.
Data Operating Mode (DOM) bits 0 and 1 representing
the type of data transfer (see Table 16)
Address bits 2 to 7 representing a 6-bit device address.
Device addressing
D
UTY CYCLE
---------------
t
L
t
+
H
t
H
100%
Preliminary specification
UDA1355H